Junctionless Nanowire Transistor (JNT): Properties and design guidelines
Junctionless Nanowire Transistor (JNT): Properties and design guidelines
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DOI：
10.1016/j.sse.2011.06.004
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发表时间：
2011-11-01
影响因子：
1.7
通讯作者：
Razavi, P.
中科院分区：
文献类型：
--
作者：
Colinge, J. P.;Kranti, A.;Razavi, P.
无结晶体管是由栅电极控制的可变电阻。硅沟道是一种重掺杂纳米线，可以完全耗尽以关闭设备。其电学特性与普通MOS-FET相同，但物理特性却大不相同。将无结纳米线晶体管(门控电阻)的导电机制与反相型和累积型MOS器件进行了比较。这种无结器件使用体导电而不是表面沟道导电。电流驱动由掺杂浓度控制，而不是由栅极电容控制。分析了阈值电压随物理参数和本征器件性能的变化规律。提出了一种在体硅上制作器件的方案。(C)2011爱思唯尔有限公司。保留所有权利。
Junctionless transistors are variable resistors controlled by a gate electrode. The silicon channel is a heavily doped nanowire that can be fully depleted to turn the device off. The electrical characteristics are identical to those of normal MOS-FETs, but the physics is quite different. Conduction mechanisms in Junctionless Nanowire Transistors (gated resistors) are compared to inversion-mode and accumulation-mode MOS devices. The junctionless device uses bulk conduction instead of surface channel conduction. The current drive is controlled by doping concentration and not by gate capacitance. The variation of threshold voltage with physical parameters and intrinsic device performance is analyzed. A scheme is proposed for the fabrication of the devices on bulk silicon. (C) 2011 Elsevier Ltd. All rights reserved.