A Unified 4/8/16/32-Point Integer IDCT Architecture for Multiple Video Coding Standards
A Unified 4/8/16/32-Point Integer IDCT Architecture for Multiple Video Coding Standards
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DOI：
10.1109/icme.2012.7
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发表时间：
2012-07
期刊：
影响因子：
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通讯作者：
Sha Shen;W. Shen;Yibo Fan;Xiaoyang Zeng
中科院分区：
文献类型：
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作者：
Sha Shen;W. Shen;Yibo Fan;Xiaoyang Zeng
4点或8点IDCT在传统的视频编码标准中被广泛使用。然而，在诸如HEVC的下一代视频标准中已经提出了更大尺寸（16/32点）的IDCT。为了满足这一要求，本文提出了一种快速的大尺寸整数IDCT算法。提出了4/8/16/32点整数IDCT的统一VLSI结构。支持MPEG-2/4、H.264、AVS、VC-1、HEVC等视频标准。无乘法器MCM（Multiple Constant Multiplication）用于4/8点IDCT。16/32点IDCT采用常规乘法器和共享技术。转置存储器使用SRAM代替传统的寄存器阵列，以进一步减少硬件开销。它可以支持4K×2K（4096×2048）30 fps视频序列的实时解码，工作频率为191 MHz，具有93 K门数和18944位SRAM。我们建议一个规范化的标准称为设计效率与以前的作品进行比较。结果表明，该设计比以前的工作效率高31%。
4 or 8-point IDCT are widely used in traditional video coding standards. However larger size (16/32-point) IDCT has been proposed in the next generation video standard such as HEVC. To fulfill this requirement, this work proposes a fast computational algorithm of large size integer IDCT. A unified VLSI architecture for 4/8/16/32-point integer IDCT is also proposed accordingly. It can support the following video standards: MPEG-2/4, H.264, AVS, VC-1 and HEVC. Multiplier less MCM (Multiple Constant Multiplication) is used for 4/8-point IDCT. The regular multipliers and sharing technique are used for 16/32-point IDCT. The transpose memory uses SRAM instead of the traditional register array in order to further reduce the hardware overhead. It can support real-time decoding of 4K×2K (4096×2048) 30fps video sequence at 191MHz working frequency, with 93K gate count and 18944-bit SRAM. We suggest a normalized criterion called design efficiency to compare with previous works. It shows that this design is 31% more efficient than previous work.