Development methodology for high-κ gate dielectrics on III–V semiconductors: GdxGa0.4−xO0.6∕Ga2O3 dielectric stacks on GaAs
Development methodology for high-κ gate dielectrics on III–V semiconductors: GdxGa0.4−xO0.6∕Ga2O3 dielectric stacks on GaAs
复制标题
III-V 族半导体上高 K 栅极电介质的开发方法：GaAs 上的 GdxGa0.4−xO0.6∕Ga2O3 电介质堆叠
DOI：
10.1116/1.1943448
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发表时间：
2005
影响因子：
1.4
通讯作者：
M. Passlack
中科院分区：
文献类型：
--
作者：
M. Passlack
提出了在III-V型半导体上开发栅极介电材料的三步方法，包括原子界面研究、氧化物模板形成和介电堆制造。第三步也是最后一步包括在GaAs上实现高κ GdxGa0.4−xO0.6∕Ga2O3介电层。本文报道了高-κ堆叠栅极氧化物，其氧化物相对介电常数为20.8±1，击穿场超过4MV∕cm，在1MV∕cm电场下漏电流为2×10−8A∕cm2， n型GaAs的界面态密度最小值Dit≤2×1011cm−2eV−1，表明Dit呈u形分布。所提出的方法可以潜在地扩展到元素半导体（如Si和Ge）和宽带隙半导体（如GaN）的高κ栅极介电发展。
A three step methodology for the development of gate dielectrics on III–V semiconductors including atomistic interface studies, oxide template formation, and dielectric stack manufacturing has been proposed. The third and final step encompasses the realization of high-κ GdxGa0.4−xO0.6∕Ga2O3 dielectric stacks on GaAs. This article reports high-κ stacked gate oxides with an oxide relative dielectric constant of 20.8±1, a breakdown field exceeding 4MV∕cm, leakage currents of ≅2×10−8A∕cm2 at an electric field of 1MV∕cm, and a broad minimum of interface state density Dit⩽2×1011cm−2eV−1 on n-type GaAs suggesting a U-shaped Dit distribution. The proposed methodology can potentially be extended to high-κ gate dielectric development on elemental semiconductors such as Si and Ge and wide band gap semiconductors such as GaN.