Sub-THz/THz Interconnect, Complement to Electrical and Optical Interconnects: Addressing Fundamental Challenges Related to Communication Distances
Sub-THz/THz Interconnect, Complement to Electrical and Optical Interconnects: Addressing Fundamental Challenges Related to Communication Distances
复制标题
亚太赫兹/太赫兹互连，对电气和光学互连的补充：解决与通信距离相关的基本挑战
DOI：
10.1109/mssc.2020.3021836
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发表时间：
2020
期刊：
影响因子：
--
通讯作者：
Q. Gu
中科院分区：
文献类型：
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作者：
Q. Gu
大数据时代见证了信息流量在十年内以26%的复合年增长率（CAGR）扩张，如图1（a）[1]，[2]所示。不断上升的数据速率会分层放大，从而缩短通信距离。也就是说，数据速率的增加从数据中心间交换到机架间、板间、芯片间和芯片内场景。近二十年来，由于不可持续的功耗，微处理器的速度一直停滞不前[4]，导致多核计算机架构。虽然多核架构减轻了数据处理功耗要求，但由于功能和系统越来越复杂，它需要更高的核与核之间的数据通信速率。图1（B）给出了输入？输出（I/O）带宽和I/O引脚数随时间的演变[5]，[6]。I/O带宽大约每两年增加2个或每五年增加10个，而由于工艺和机械限制，I/O引脚数的增长速度要小得多，每五年增加1.7个。这导致I/O带宽需求和功能之间的差距越来越大，众所周知的是互连差距，这是十多年来一直存在的主要挑战。
The big data era has witnessed expansion of information traffic at a 26% compound annual growth rate (CAGR) during one decade, as shown in Figure 1(a) [1], [2]. Rising data rates magnify hierarchically down to shorter communication distances. That is, data rate increases are exchanged from interdata centers to interrack, interboard, interchip, and intrachip scenarios. For almost two decades, microprocessor speeds have been stalled due to unsustainable power consumption [4], resulting in multicore computer architectures. Although the multicore architecture mitigates the data processing power consumption requirement, it demands higher data communication rates from core to core, due to increasingly complex functionalities and systems. Figure 1(b) presents the input?output (I/O) bandwidth and I/O pin number evolution through time [5], [6]. The I/O bandwidth increases by approximately 2 every two years or 10 every five years, while the I/O pin number grows at a much smaller rate, 1.7 every five years, because of process and mechanical constraints. This results in a widening gap between I/O bandwidth requirements and capabilities, notoriously named the interconnect gap, which has been a major and long-standing challenge for more than a decade.
高密度、大规模外差传感 CMOS 阵列：采用分散式架构的 240 GHz、32 单元接收器
DOI：
10.1109/rfic.2018.8428843
发表时间：
2018
期刊：
2018 IEEE Radio Frequency Integrated Circuits Symposium (RFIC
影响因子：
--
作者：
Hu, Zhi;Wang, Cheng;Han, Ruonan
通讯作者：
Han, Ruonan