Advanced Fabrication Processes for Superconducting Very Large-Scale Integrated Circuits
Advanced Fabrication Processes for Superconducting Very Large-Scale Integrated Circuits
复制标题
超导超大规模集成电路的先进制造工艺
DOI：
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发表时间：
2015
影响因子：
1.8
通讯作者：
M. Gouker
中科院分区：
文献类型：
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作者：
S. K. Tolpygo;V. Bolkhovsky;T. Weir;A. Wynn;D. Oates;L. Johnson;M. Gouker
我们回顾了麻省理工学院林肯实验室最近开发的用于制造200毫米晶圆上大规模集成的单通量量子（SFQ）数字电路的8- nb层全平面化工艺的两个先进节点的显著特征：SFQ4ee和SFQ5ee节点，其中“ee”表示该工艺被调整为节能的SFQ电路。前者具有8个最小特征尺寸为0.5 μm的超导层和用于电路电阻的2-Ω/sq Mo层。后者具有9个超导层：8个最小特征尺寸为350 nm的Nb布线层和一个具有高动态电感（约8 pH/sq）的薄超导MoNx层（Tc ~ 7.5 K），用于形成紧凑的电感器。6个-Ω/sq平面电阻器采用低氮含量的非超导（Tc < 2k） MoNx层，用于约瑟夫森结（JJs）的分流和偏置。另一电阻层被加入形成层间百欧姆范围的三明治型电阻，用于从逻辑单元的超导回路中释放不需要的通量量子。两个工艺节点都使用Au/Pt/Ti接触金属化来进行芯片封装。该技术采用一层Nb/AlOx-Al/Nb JJs，临界电流密度Jc为100 μA/μm2，最小直径为700 nm。电路图形由248nm光刻和高密度等离子体刻蚀确定。所有的电路层都采用化学机械平面化SiO2层间介质。本文提出并讨论了以下结果和主题：JJs下表面形貌对其性能和可重复性的影响，Ic和Jc的靶向性，溶解在Nb中的氢的影响，电阻层和高动感层的MoNx性能，以及毫欧姆范围电阻器技术。
We review the salient features of two advanced nodes of an 8-Nb-layer fully planarized process developed recently at MIT Lincoln Laboratory for fabricating single flux quantum (SFQ) digital circuits with very large-scale integration on 200-mm wafers: the SFQ4ee and SFQ5ee nodes, where “ee” denotes that the process is tuned for energy-efficient SFQ circuits. The former has eight superconducting layers with 0.5-μm minimum feature size and a 2-Ω/sq Mo layer for circuit resistors. The latter has nine superconducting layers: eight Nb wiring layers with the minimum feature size of 350 nm and a thin superconducting MoNx layer (Tc ~ 7.5 K) with high kinetic inductance (about 8 pH/sq) for forming compact inductors. A nonsuperconducting (Tc <; 2 K) MoNx layer with lower nitrogen content is used for 6-Ω/sq planar resistors for shunting and biasing of Josephson junctions (JJs). Another resistive layer is added to form interlayer sandwich-type resistors of milliohm range for releasing unwanted flux quanta from superconducting loops of logic cells. Both process nodes use Au/Pt/Ti contact metallization for chip packaging. The technology utilizes one layer of Nb/AlOx-Al/Nb JJs with critical current density Jc of 100 μA/μm2 and minimum diameter of 700 nm. Circuit patterns are defined by 248-nm photolithography and high-density plasma etching. All circuit layers are fully planarized using chemical mechanical planarization of SiO2 interlayer dielectric. The following results and topics are presented and discussed: the effect of surface topography under the JJs on the their properties and repeatability, Ic and Jc targeting, effect of hydrogen dissolved in Nb, MoNx properties for the resistor layer and for high-kinetic-inductance layer, and technology of milliohm-range resistors.