FPGA-based measurement and evaluation of power analysis attack resistant asynchronous S-Box
FPGA-based measurement and evaluation of power analysis attack resistant asynchronous S-Box
复制标题
基于FPGA的抗功耗分析攻击异步S-Box测量与评估
DOI：
10.1109/imtc.2011.5944288
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发表时间：
2011
期刊：
影响因子：
--
通讯作者：
Minsu Choi
中科院分区：
文献类型：
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作者：
Jun Wu;Yiyu Shi;Minsu Choi
本文展示了最近提出的针对AES加密系统的低功率侧通道攻击（SCA）抗异步S-box设计。指定的侧通道攻击标准评估FPGA板（Sasebo-GII）用于实施设计。该板包含两个Xilinx FPGA，以分别执行加密功能和配置函数。这样可以防止配置电路的功率轨迹干扰加密电路的功率轨迹，以便可以公平地进行制作/抵抗功率分析攻击的测量值。所提出的设计是免费的，并且具有平坦的功率峰，因为它基于称为Null Justince Logic（NCL）的延迟不敏感的逻辑范式。现有同步S-box设计与提出的异步设计之间的比较在各个方面进行；速度，面积，总功耗以及差分功率分析（DPA）攻击的结果，这是最有力的加密分析之一，可以提取加密设备的秘密键。实验结果表明，所提出的异步S-box对DPA攻击具有抗性，并且比同步对应物具有较低的功耗。
This paper demonstrates a recently proposed low-power side channel attack (SCA) resistant asynchronous S-Box design for the AES crypto-systems. A specified side channel attack standard evaluation FPGA board (SASEBO-GII) is used to implement the design. This board includes two Xilinx FPGAs to perform the cryptographic function and the configuration function separately. This prevents the power trace of the configuration circuit from interfering with the power trace of the cryptographic circuit, so that the measurements of making/resisting power analysis attack can be done fairly. The proposed design is clock free and has flatter power peaks since it is based on a delay-insensitive logic paradigm referred to as null convention logic (NCL). Comparisons between the existing synchronous S-Box design and the proposed asynchronous design are performed in the various aspects; speed, area, total power consumption, and results of differential power analysis (DPA) attack, one of the most powerful cryptanalysis that could extract the secret keys of cryptographic devices. Experimental results shows that the proposed asynchronous S-Box is resistant to DPA attacks and has a lower power consumption than its synchronous counterpart.