Bit-fixing in pseudorandom sequences for scan BIST
Bit-fixing in pseudorandom sequences for scan BIST
复制标题
用于扫描 BIST 的伪随机序列中的位固定
DOI:
10.1109/43.918212
复制
发表时间:
2001
期刊:
影响因子:
--
通讯作者:
E. McCluskey
中科院分区:
文献类型:
--
作者:
N. Touba;E. McCluskey
A low-overhead scheme for achieving complete (100%) fault coverage during built-in self test of circuits with scan is presented. It does not require modifying the function logic and does not degrade system performance (beyond using scan). Deterministic test cubes that detect the random-pattern-resistant (r.p.r.) faults are embedded in a pseudorandom sequence of bits generated by a linear feedback shift register (LFSR). This is accomplished by altering the pseudorandom sequence by adding logic at the LFSR's serial output to "fix" certain bits. A procedure for synthesizing the bit-fixing logic for embedding the test cubes is described. Experimental results indicate that complete fault coverage can be obtained with low hardware overhead. Further reduction in overhead is possible by using a special correlating automatic test pattern generation procedure that is described for finding test cubes for the r.p.r. faults in a way that maximizes bitwise correlation.