Bit-fixing in pseudorandom sequences for scan BIST

Bit-fixing in pseudorandom sequences for scan BIST
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用于扫描 BIST 的伪随机序列中的位固定

DOI:
10.1109/43.918212
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发表时间:
2001
期刊:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
影响因子:
--
通讯作者:
E. McCluskey
E. McCluskey
中科院分区:
--
文献类型:
--
作者:
N. Touba;E. McCluskey

文献摘要

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提出了一种在带扫描电路的内建自测试过程中实现完全(100%)故障覆盖的低开销方案。它不需要修改功能逻辑,也不会降低系统性能(使用扫描之外)。确定性测试立方体,检测抗随机模式(R.P.R.)故障嵌入在线性反馈移位寄存器(LFSR)生成的伪随机位序列中。这是通过更改伪随机序列来实现的,方法是在LFSR的串行输出端添加逻辑以“修复”某些位。描述了一种用于合成用于嵌入测试立方体的位固定逻辑的过程。实验结果表明,该方法能够以较低的硬件开销获得完全的故障覆盖。通过使用特殊的关联自动测试模式生成过程来进一步减少开销是可能的,所述特殊关联自动测试模式生成过程用于寻找用于R.P.R.的测试立方体。错误以最大化逐位相关性的方式。
A low-overhead scheme for achieving complete (100%) fault coverage during built-in self test of circuits with scan is presented. It does not require modifying the function logic and does not degrade system performance (beyond using scan). Deterministic test cubes that detect the random-pattern-resistant (r.p.r.) faults are embedded in a pseudorandom sequence of bits generated by a linear feedback shift register (LFSR). This is accomplished by altering the pseudorandom sequence by adding logic at the LFSR's serial output to "fix" certain bits. A procedure for synthesizing the bit-fixing logic for embedding the test cubes is described. Experimental results indicate that complete fault coverage can be obtained with low hardware overhead. Further reduction in overhead is possible by using a special correlating automatic test pattern generation procedure that is described for finding test cubes for the r.p.r. faults in a way that maximizes bitwise correlation.