Sparseloop: An Analytical Approach To Sparse Tensor Accelerator Modeling
Sparseloop: An Analytical Approach To Sparse Tensor Accelerator Modeling
复制标题
DOI：
10.1109/micro56248.2022.00096
复制
发表时间：
2022-05
期刊：
影响因子：
--
通讯作者：
Yannan Nellie Wu;Po-An Tsai;A. Parashar;V. Sze;J. Emer
中科院分区：
文献类型：
--
作者：
Yannan Nellie Wu;Po-An Tsai;A. Parashar;V. Sze;J. Emer
近年来，已经提出了许多加速器来有效地处理稀疏张量代数应用（例如，稀疏神经网络）。然而，这些建议是一个大而多样的设计空间中的单一点。缺乏对这些稀疏张量加速器的系统描述和建模支持阻碍了硬件设计人员进行高效和有效的设计空间探索。本文首先提出了一个统一的分类系统描述不同的稀疏张量加速器设计空间。基于所提出的分类，然后介绍了Sparseloop，这是第一个快速，准确，灵活的分析建模框架，可以对稀疏张量加速器进行早期评估和探索。Sparseloop提供了大量的架构规范，包括各种各样的流和稀疏加速特性（例如，消除基于零的计算）。使用这些规范，Sparseloop评估设计的处理速度和能源效率，同时考虑所采用的并行计算引起的数据移动和计算，包括使用随机密度模型的稀疏加速功能带来的节省和开销。在代表性的加速器设计和工作负载中，Sparseloop的建模速度比周期级模拟快2000倍以上，保持相对性能趋势，并实现0.1%至8%的平均误差。本文还介绍了Sparseloop在不同加速器设计流程中的示例用例，以揭示重要的设计见解。
In recent years, many accelerators have been proposed to efficiently process sparse tensor algebra applications (e.g., sparse neural networks). However, these proposals are single points in a large and diverse design space. The lack of systematic description and modeling support for these sparse tensor accelerators impedes hardware designers from efficient and effective design space exploration. This paper first presents a unified taxonomy to systematically describe the diverse sparse tensor accelerator design space. Based on the proposed taxonomy, it then introduces Sparseloop, the first fast, accurate, and flexible analytical modeling framework to enable early-stage evaluation and exploration of sparse tensor accelerators. Sparseloop comprehends a large set of architecture specifications, including various dataflows and sparse acceleration features (e.g., elimination of zero-based compute). Using these specifications, Sparseloop evaluates a design’s processing speed and energy efficiency while accounting for data movement and compute incurred by the employed dataflow, including the savings and overhead introduced by the sparse acceleration features using stochastic density models. Across representative accelerator designs and workloads, Sparseloop achieves over 2000× faster modeling speed than cycle-level simulations, maintains relative performance trends, and achieves 0.1% to 8% average error. The paper also presents example use cases of Sparseloop in different accelerator design flows to reveal important design insights.