A preactivating mechanism for a VT-CMOS cache using address prediction
A preactivating mechanism for a VT-CMOS cache using address prediction
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一种使用地址预测的 VT-CMOS 缓存预激活机制
DOI：
10.1145/566408.566472
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发表时间：
2002
期刊：
影响因子：
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通讯作者：
T. Shimada
中科院分区：
文献类型：
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作者：
R. Fujioka;K. Katayama;R. Kobayashi;H. Ando;T. Shimada
同时实现高性能和低功耗已经成为一个重要的要求。动态泄漏截止（DLC）方案按需通过线控制晶体管的阈值电压，是一种潜在地满足高速缓存的要求的技术。然而，传统的DLC导致访问时间显著延长，因此处理器性能不可接受地降低。本文提出了一种机制，抑制性能下降的预激活缓存线访问请求前使用地址预测。我们的评估结果表明，显着的性能改善，实现了几乎没有增加的功耗。
It has become an important requirement to achieve high performance and low-power consumption at the same time. The dynamic leakage cut-off (DLC) scheme, which controls transistors' threshold voltage by the line on demand, is a technique that potentially satisfies that requirement for a cache. Yet, conventional DLC causes access time to significantly lengthen, and consequently processor performance is unacceptably degraded. This paper proposes a mechanism that suppresses the performance degradation by preactivating cache lines using address prediction before access requests. Our evaluation results show significant performance improvements are achieved with little increase of power consumption.