A Hybrid Approach for Mapping Conjugate Gradient onto an FPGA-Augmented Reconfigurable Supercomputer
A Hybrid Approach for Mapping Conjugate Gradient onto an FPGA-Augmented Reconfigurable Supercomputer
复制标题
将共轭梯度映射到 FPGA 增强可重构超级计算机的混合方法
DOI：
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发表时间：
2006
期刊：
影响因子：
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通讯作者：
Richard D. Anderson
中科院分区：
文献类型：
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作者：
G. R. Morris;V. Prasanna;Richard D. Anderson
超级计算机公司，如Cray， Silicon Graphics和SRC Computers现在提供可重构计算机（RC）系统，该系统将通用处理器（gpp）与现场可编程门阵列（fpga）相结合。实际上，fpga可以被编程为特定于应用程序的处理器。这些令人兴奋的超级计算机允许最终用户创建针对每个问题的计算密集型部分的自定义计算架构。本文描述了一种参数化、并行化、深度流水线、双fpga、IEEE-754 64位浮点设计，用于在fpga增强RC上加速共轭梯度迭代法。基于fpga的元件是通过混合方法开发的，该方法使用高级语言（HLL）到硬件描述语言（HDL）编译器与定制的基于vhdl的浮点组件相结合。该设计的参考版本在当代RC上实现。实际运行时性能数据将fpga增强CG与软件版本进行了比较，结果表明基于fpga的版本比软件版本运行速度快1.3倍。估计表明，该设计可以在下一代RC上实现4倍的加速
Supercomputer companies such as Cray, Silicon Graphics, and SRC Computers now offer reconfigurable computer (RC) systems that combine general-purpose processors (GPPs) with field-programmable gate arrays (FPGAs). The FPGAs can be programmed to become, in effect, application-specific processors. These exciting supercomputers allow end-users to create custom computing architectures aimed at the computationally intensive parts of each problem. This report describes a parameterized, parallelized, deeply pipelined, dual-FPGA, IEEE-754 64-bit floating-point design for accelerating the conjugate gradient (CG) iterative method on an FPGA-augmented RC. The FPGA-based elements are developed via a hybrid approach that uses a high-level language (HLL)-to-hardware description language (HDL) compiler in conjunction with custom-built, VHDL-based, floating-point components. A reference version of the design is implemented on a contemporary RC. Actual run time performance data compare the FPGA-augmented CG to the software-only version and show that the FPGA-based version runs 1.3 times faster than the software version. Estimates show that the design can achieve a 4 fold speedup on a next-generation RC