PRET DRAM controller: Bank privatization for predictability and temporal isolation
PRET DRAM controller: Bank privatization for predictability and temporal isolation
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PRET DRAM 控制器：银行私有化以实现可预测性和时间隔离
DOI：
10.1145/2039370.2039388
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发表时间：
2011
期刊：
影响因子：
--
通讯作者：
Edward A. Lee
中科院分区：
文献类型：
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作者：
Jan Reineke;Isaac Liu;Hiren D. Patel;Sungjun Kim;Edward A. Lee
硬实时嵌入式系统采用高容量存储器，如动态ram (dram)，以应对现代设计中不断增加的数据和代码大小。然而，到目前为止，内存控制器的设计主要集中在提高平均情况下的性能。因此，内存访问的延迟是不可预测的，这使得硬实时嵌入式系统所需的最坏情况执行时间分析变得复杂。我们的工作引入了一种新颖的DRAM控制器设计，它是可预测的，并显著降低了最坏情况下的访问延迟。我们的方法不是将DRAM设备视为只能作为一个整体共享的一个资源，而是将其视为可以在一个或多个客户机之间单独共享的多个资源。我们按照DRAM设备的内部结构划分物理地址空间，即，它的行列和银行，并交错访问该分区的块。这消除了对设备内共享资源的争用，使得访问在时间上是可预测的，并且在时间上是隔离的。本文介绍了我们的DRAM控制器设计及其与称为PTARM的精确定时（PRET）架构的集成。我们给出了所提出控制器的延迟和吞吐量的分析边界，并通过仿真验证了这些边界。
Hard real-time embedded systems employ high-capacity memories such as Dynamic RAMs (DRAMs) to cope with increasing data and code sizes of modern designs. However, memory controller design has so far largely focused on improving average-case performance. As a consequence, the latency of memory accesses is unpredictable, which complicates the worst-case execution time analysis necessary for hard real-time embedded systems. Our work introduces a novel DRAM controller design that is predictable and that significantly reduces worst-case access latencies. Instead of viewing the DRAM device as one resource that can only be shared as a whole, our approach views it as multiple resources that can be shared between one or more clients individually. We partition the physical address space following the internal structure of the DRAM device, i.e., its ranks and banks, and interleave accesses to the blocks of this partition. This eliminates contention for shared resources within the device, making accesses temporally predictable and temporally isolated. This paper describes our DRAM controller design and its integration with a precision-timed (PRET) architecture called PTARM. We present analytical bounds on the latency and throughput of the proposed controller, and confirm these via simulation.