RapidSmith 2: A Framework for BEL-level CAD Exploration on Xilinx FPGAs
RapidSmith 2: A Framework for BEL-level CAD Exploration on Xilinx FPGAs
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RapidSmith 2：Xilinx FPGA 上的 BEL 级 CAD 探索框架
DOI：
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发表时间：
2015
期刊：
影响因子：
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通讯作者：
B. Hutchings
中科院分区：
文献类型：
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作者：
Travis Haroldsen;B. Nelson;B. Hutchings
RapidSmith是一个开源框架，允许探索Xilinx器件FPGA CAD流程的新方法。然而，RapidSmith对于在切片水平以下操作设计的支持很差。在本文中，我们强调了RapidSmith启用的许多项目，并将其扩展到“RapidSmith 2”中，这些扩展将LUT和触发器暴露在定制的CAD工具中进行直接操作。为了证明RapidSmith 2的实用性，我们提出了工作的结果，以确定必须聚集在一起的设计和工具，做预包装聚类。
RapidSmith is an open-source framework that allows for the exploration of novel approaches to the FPGA CAD flow for Xilinx devices. However, RapidSmith has poor support for manipulating designs below the slice level. In this paper, we highlight many of the projects RapidSmith enables and present extensions incorporated into "RapidSmith 2" that expose LUTs and flip-flops for direct manipulation in custom-built CAD tools. To demonstrate the utility of RapidSmith 2 we present the results of work to identify BELs in a design which must be clustered together and a tool that does pre-packing clustering accordingly.