Self-aligned, vertical-channel, polymer field-effect transistors
Self-aligned, vertical-channel, polymer field-effect transistors
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DOI：
10.1126/science.1081279
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发表时间：
2003-03-21
期刊：
影响因子：
56.9
通讯作者：
Sirringhaus, H
中科院分区：
文献类型：
--
作者：
Stutzmann, N;Friend, RH;Sirringhaus, H
在柔性塑料基板上制造高性能共轭聚合物晶体管电路需要能够以亚微米分辨率定义关键特征的图案化技术。我们使用固态压印来生产具有亚微米临界特征的平面和垂直配置的聚合物场效应晶体管。压花用于将垂直侧壁受控微切割成聚合物多层结构而不涂抹。在柔性聚对苯二甲酸乙二酯衬底上制备了垂直沟道聚合物场效应晶体管，其中0.7至0.9微米的临界沟道长度由旋涂绝缘层的厚度限定。通过喷墨印刷自对准栅电极以使重叠电容最小化，喷墨印刷使用压印凹槽来限定表面能图案。
The manufacture of high-performance, conjugated polymer transistor circuits on flexible plastic substrates requires patterning techniques that are capable of defining critical features with submicrometer resolution. We used solid-state embossing to produce polymer field-effect transistors with submicrometer critical features in planar and vertical configurations. Embossing is used for the controlled microcutting of vertical sidewalls into polymer multilayer structures without smearing. Vertical-channel polymer field-effect transistors on flexible poly(ethylene terephthatate) substrates were fabricated, in which the critical channel length of 0.7 to 0.9 micrometers was defined by the thickness of a spin-coated insulator layer. Gate electrodes were self-aligned to minimize overlap capacitance by inkjet printing that used the embossed grooves to define a surface-energy pattern.