Efficient footprint caching for Tagless DRAM Caches
Efficient footprint caching for Tagless DRAM Caches
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无标签 DRAM 缓存的高效占用空间缓存
DOI：
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发表时间：
2016
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通讯作者：
Jae W. Lee
中科院分区：
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作者：
Hakbeom Jang;Yongjun Lee;JongWon Kim;Youngsok Kim;Jang;Jinkyu Jeong;Jae W. Lee
高效的高速缓存标签管理是大型封装内DRAM高速缓存的主要设计目标。最近，已经提出了无标签DRAM高速缓存（TDC）以从管芯上SRAM和封装内DRAM两者完全消除标签结构，标签结构是未来多千兆字节DRAM高速缓存的主要可扩展性瓶颈。然而，TDC对DRAM高速缓冲存储器块大小施加与OS页大小相同的约束（例如，4KB），因为它采用统一的方法来进行地址转换和缓存标记管理。以页面粒度进行缓存或基于页面的缓存会通过过度提取页面内实际上未使用的块而导致显著的封装外DRAM带宽浪费。占用空间缓存是解决这个问题的有效方法，它只提取那些在DRAM缓存中的页面生命周期内可能会被触及的块，称为页面占用空间。在本文中，我们证明TDC开辟了独特的机会，实现高效的足迹缓存具有更高的预测精度和更低的硬件成本比原来的足迹缓存方案。由于TDC中没有高速缓存标签，因此在TLB而不是高速缓存标签阵列处跟踪高速缓存页面的占用空间，从而产生比原始设计低得多的管芯上存储开销。此外，当缓存页面被逐出时，其占用空间将被存储在对应的页表条目中，而不是辅助的管芯上结构（即，足迹历史表），以防止不同页面之间的足迹颠簸，从而在足迹预测中产生更高的准确性。由此产生的设计，称为足迹增强无标签DRAM缓存（F-TDC），显着提高TDC的带宽效率，从而提高其性能和能源效率。我们对基于3D SOI-硅通孔的封装内DRAM的评估表明，与没有占用空间缓存的最先进TDC相比，封装外带宽平均减少了32.0%，从而将IPC和EDP分别提高了17.7%和25.4%。
Efficient cache tag management is a primary design objective for large, in-package DRAM caches. Recently, Tagless DRAM Caches (TDCs) have been proposed to completely eliminate tagging structures from both on-die SRAM and in-package DRAM, which are a major scalability bottleneck for future multi-gigabyte DRAM caches. However, TDC imposes a constraint on DRAM cache block size to be the same as OS page size (e.g., 4KB) as it takes a unified approach to address translation and cache tag management. Caching at a page granularity, or page-based caching, incurs significant off-package DRAM bandwidth waste by over-fetching blocks within a page that are not actually used. Footprint caching is an effective solution to this problem, which fetches only those blocks that will likely be touched during the page's lifetime in the DRAM cache, referred to as the page's footprint. In this paper we demonstrate TDC opens up unique opportunities to realize efficient footprint caching with higher prediction accuracy and a lower hardware cost than the original footprint caching scheme. Since there are no cache tags in TDC, the footprints of cached pages are tracked at TLB, instead of cache tag array, to incur much lower on-die storage overhead than the original design. Besides, when a cached page is evicted, its footprint will be stored in the corresponding page table entry, instead of an auxiliary on-die structure (i.e., Footprint History Table), to prevent footprint thrashing among different pages, thus yielding higher accuracy in footprint prediction. The resulting design, called Footprint-augmented Tagless DRAM Cache (F-TDC), significantly improves the bandwidth efficiency of TDC, and hence its performance and energy efficiency. Our evaluation with 3D Through-Silicon-Via-based in-package DRAM demonstrates an average reduction of off-package bandwidth by 32.0%, which, in turn, improves IPC and EDP by 17.7% and 25.4%, respectively, over the state-of-the-art TDC with no footprint caching.