CMOS SOCs at 100 GHz: System Architectures, Device Characterization, and IC Design Examples
CMOS SOCs at 100 GHz: System Architectures, Device Characterization, and IC Design Examples
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100 GHz 的 CMOS SOC：系统架构、器件表征和 IC 设计示例
DOI：
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发表时间：
2007
期刊：
影响因子：
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通讯作者：
Ming
中科院分区：
文献类型：
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作者：
S. Voinigescu;S. Nicolson;M. Khanpour;K. W. Tang;K. Yau;N. Seyedfathi;A. Timonov;A. Nachman;G. Eleftheriades;P. Schvan;Ming
本文研究了90 nm和65 nm GP和LP CMOS工艺在60 GHz至100 GHz范围内的SOC应用的适用性。提供了系统架构和收发器构建块的示例，其强调了如果CMOS要在60 GHz以上与SiGe BiCMOS竞争，则需要积极缩放的GP CMOS和低VT晶体管。这一要求与2005-ITRS建议将LP CMOS用于RF应用相冲突。
This paper investigates the suitability of 90nm and 65nm GP and LP CMOS technology for SOC applications in the 60GHz to 100GHz range. Examples of system architectures and transceiver building blocks are provided which emphasize the need for aggressively scaled GP CMOS and low-VT transistors if CMOS is to compete with SiGe BiCMOS above 60 GHz. This requirement is in conflict with the 2005-ITRS proposal to use LP CMOS for RF applications.