Exploring Heterogeneous-ISA Core Architectures for High-Performance and Energy-Efficient Mobile SoCs

Exploring Heterogeneous-ISA Core Architectures for High-Performance and Energy-Efficient Mobile SoCs
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探索高性能、高能效移动 SoC 的异构 ISA 核心架构

DOI:
10.1145/3060403.3060408
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发表时间:
2017
期刊:
Proceedings of the Great Lakes Symposium on VLSI 2017
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通讯作者:
L. John
L. John
中科院分区:
--
文献类型:
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作者:
Wooseok Lee;Dam Sunwoo;C. D. Emmons;A. Gerstlauer;L. John

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在本文中,我们探讨了通过为核心提供受限功能来提高能源效率的机会,但不一定会影响性能。我们的目标是通过移除对复杂但执行频率较低的指令的支持来实现这一目标,因为实际工作负载使用的指令混合通常存在严重偏差。我们通过分析ARM ISA中的指令子集及其在微架构中相应的逻辑负担来研究哪些指令值得删除。我们提出了一种异构isa系统,在不降低性能的情况下实现能源效率,使用结合了完整和减少isa核心的系统架构。结果表明,通过提供异构isa核心的灵活性,所提出的系统可以平均提高12%的能源效率,对于不需要NEON支持的应用可以提高15%的能源效率,所有这些都没有性能开销。
In this paper, we explore opportunities to increase energy efficiency by providing cores with restricted functionality, but without necessarily impacting performance. We aim to achieve this by removing support for complex but less frequently executed instructions since instruction mixes used by real-world workloads are often heavily biased. We investigate which instructions are worthwhile to remove by analyzing a subset of instructions in the ARM ISA and their corresponding logic burden in the microarchitecture. We propose a heterogeneous-ISA system to achieve energy efficiency without performance degradation using a system architecture that combines both full- and reduced-ISA cores. Results show that by providing the flexibility of heterogeneous-ISA cores, the proposed system can improve energy efficiency by 12% on average and up to 15% for applications that do not require NEON support, all without performance overhead.