Pulser gating: A clock gating of pulsed-latch circuits
Pulser gating: A clock gating of pulsed-latch circuits
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DOI：
10.1109/aspdac.2011.5722182
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发表时间：
2011-01
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影响因子：
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通讯作者：
Sangmin Kim;Inhak Han;Seungwhun Paik;Youngsoo Shin
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文献类型：
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作者：
Sangmin Kim;Inhak Han;Seungwhun Paik;Youngsoo Shin
脉冲锁存器由于其较小的电容和简单的时序模型，是低功耗ASIC设计的理想时序元件。脉冲锁存电路的时钟选通可以通过选通脉冲发生器（或脉冲发生器）来实现，我们称之为脉冲发生器选通。首次提出了脉冲发生器选通综合问题。给定一个门级网表，并给出锁存器的位置，首先提取每个锁存器的门控函数，合并门控函数以减少额外的逻辑量，同时门控概率不会牺牲太多。我们还必须考虑锁存器的接近度，因为由合并选通功能选通的脉冲发生器及其锁存器必须物理上接近以安全输送脉冲。启发式算法，考虑所有三个因素（门控功能的相似性，文字计数，以实现门控功能，和锁存器的接近度）提出和评估方面的节能和面积使用45纳米技术。
A pulsed-latch is an ideal sequencing element for low-power ASIC designs due to its smaller capacitance and simple timing model. Clock gating of pulsed-latch circuits can be realized by gating a pulse generator (or pulser), which we call pulser gating. The problem of pulser gating synthesis is formulated for the first time. Given a gate-level netlist with location of latches, we first extract the gating function of each latch; the gating functions are merged to reduce the amount of extra logic while gating probability is not sacrificed too much. We also have to take account of proximity of latches, because a pulser, which is gated by merged gating function, and its latches have to be physically close for safe delivery of pulse. The heuristic algorithm that considers all three factors (similarity of gating functions, literal count to implement gating functions, and proximity of latches) is proposed and assessed in terms of power saving and area using 45-nm technology.