An Automated Design Flow for NoC-based MPSoCs on FPGA
An Automated Design Flow for NoC-based MPSoCs on FPGA
复制标题
FPGA 上基于 NoC 的 MPSoC 的自动化设计流程
DOI：
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发表时间：
2008
期刊：
影响因子：
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通讯作者：
Leandro Fiorin
中科院分区：
文献类型：
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作者：
S. Lukovic;Leandro Fiorin
嵌入式设备市场的动态增加使得缩短面市时间成为现代嵌入式系统设计中最具挑战性的任务之一。多处理器片上系统(MPSoCs)的复杂性迅速增加，片上网络(NoCs)作为一种设计策略应运而生。为了在开发阶段快速生成这些平台，需要一个完整的设计流程。另一方面，现代的现场可编程门阵列为快速和低成本的原型制造提供了可能，代表了对这些需求的有效响应。本文基于Xilinx Embedded Development Kit(EDK)的设计流程，提出了一种基于片上网络的MPSoC生成框架。该工具为系统设计人员提供了轻松、快速地生成有助于测试、调试和验证目的的所需架构的可能性。我们的集成设计流程将系统的文本描述作为输入，并生成配置位流文件作为最终结果。该框架已经在Xilinx Virtex-II Pro板上进行了测试和验证。
Increased dynamics of the embedded devices market makes reduced time-to-market emerge as one of most challenging tasks in modern embedded system design. The complexity of Multiprocessor Systems-on-Chip (MPSoCs) rapidly increases and Networks-on-Chips (NoCs) have emerged as design strategy to cope with it. In order to allow fast generation of these platforms in the development phase, a full design flow is required. On the other hand, modern FPGAs provide the possibility for fast and low-cost prototyping, representing an efficient response to these needs. In this paper we present a framework, based on the Xilinx Embedded Development Kit (EDK) design flow, for the generation of MPSoCs based on NoCs. The tool provides system designers with the possibility to easily and quickly generate desired architectures that can be helpful for testing, debugging and verifying purposes. Our integrated design flow takes as input a textual description of the system and produces as final result a configuration bitstream file. The framework has been tested and verified on a Xilinx Virtex-II Pro board.