An algorithm for synthesis of system-level interface circuits
An algorithm for synthesis of system-level interface circuits
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一种系统级接口电路综合算法
DOI：
10.1109/iccad.1996.569835
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发表时间：
1996
期刊：
影响因子：
--
通讯作者：
C. Liu
中科院分区：
文献类型：
--
作者：
Ki;Rajesh K. Gupta;C. Liu
我们描述了一种用于嵌入式系统组件（例如微处理器、存储器 ASIC 和具有固定接口的网络子系统）的接口电路的合成和优化的算法。该算法接受两个系统组件的时序特性作为输入，并生成组合接口（粘合逻辑）电路。该算法由两部分组成。在第一部分中，我们采用 0/1 ILP 公式确定接口电路中的直接引脚对引脚连接，以最大限度地减少布线面积和动态功耗。在第二部分中，我们利用系统组件的时序图确定接口电路中的逻辑子电路。所提出的算法已在软件包 SYNTERFACE 中实现。实验结果证明了该算法的有效性。
We describe an algorithm for the synthesis and optimization of interface circuits for embedded system components such as microprocessors, memory ASIC, and network subsystems with fixed interfaces. The algorithm accepts the timing characteristics of two system components as input, and generates a combinational interface (glue logic) circuit. The algorithm consists of two parts. In the first part, we determine the direct pin-to-pin connections in the interface circuit employing a 0/1 ILP formulation to minimize wiring area and dynamic power consumption. In the second part, we determine logic subcircuits in the interface circuit, utilizing the timing diagrams of the system components. The proposed algorithm has been implemented in a software package SYNTERFACE. Experimental results are presented to demonstrate the effectiveness of the algorithm.