A novel N-bit SAR implementation for All-Digital DLL circuits
A novel N-bit SAR implementation for All-Digital DLL circuits
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DOI：
10.1109/icm.2010.5696179
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发表时间：
2010-12
期刊：
影响因子：
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通讯作者：
Al-Hussein A. El-Shafie;S.E.-D. Habib
中科院分区：
文献类型：
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作者：
Al-Hussein A. El-Shafie;S.E.-D. Habib
A novel implementation of the N-bit Successive Approximation Register (SAR) Delay Locked Loop (DLL) is proposed with a significantly reduced hardware overhead relative to the conventional approach. The hardware overhead for the proposed 2-bit SAR scheme is only 25% of that for the conventional 2-bit SAR scheme. In this work, a complete All-Digital DLL (ADDLL) design implementing the proposed 2-bit scheme is developed. All design units are first described in Verilog, and then mapped to silicon using the IBM 0.13µm Artisan standard cell library. The proposed design has an active area of 0.009mm2 and can operate from 140MHz to 800MHz with a locking time of six input clock cycles only.
