A 281-nW 43.3 fJ/conversion-step 8-ENOB 25-kS/s asynchronous SAR ADC in 65nm CMOS for biomedical applications
A 281-nW 43.3 fJ/conversion-step 8-ENOB 25-kS/s asynchronous SAR ADC in 65nm CMOS for biomedical applications
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采用 65nm CMOS 的 281nW 43.3 fJ/转换步 8-ENOB 25kS/s 异步 SAR ADC，适用于生物医学应用
DOI：
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发表时间：
2013
期刊：
影响因子：
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通讯作者：
Y. Y. Lam
中科院分区：
文献类型：
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作者：
C. Yuan;Y. Y. Lam
介绍了一种用于生物医学的低功耗25KS/S逐次逼近寄存器模数转换器。ADC在DAC中采用了一种新颖的低功耗和面积高效的三电平开关方案。与传统的合成孔径雷达模数转换器相比，其平均开关能量和总电容分别降低了97%和75%。采用异步设计，消除了传统的N倍采样率的系统时钟。此外，基于延迟的内部时钟发生器产生的高速信号允许真单相时钟(TSPC)D触发器(DFF)用于低速生物医学应用。该模数转换器的工作范围为0~1 MS/S，采用联华65 nm 1P6M工艺制作的模数转换器在25kS/S下性能最好，SNDR为50.1dBSFDR为55.3dBSFDR。该模数转换器工作在1 V电源和25 kS/S下，功耗为281 nW，FOM为43.3fJ/转换步长。芯片芯片面积为145μm×120μm。
This paper describes a low-power 25-kS/s successive approximation register (SAR) analog-to-digital converter (ADC) for biomedical applications. The ADC employs a novel low-energy and area-efficient tri-level switching scheme in the DAC. Compared to the conventional SAR ADC, the average switching energy and total capacitance are reduced by 97% and 75%, respectively. Asynchronous design is implemented to eliminate the conventional system clock which is N-time of sampling rate. Furthermore, a delay-based internal clock generator produces a high-speed signal which allows True Single Phase Clock (TSPC) D Flip-flop (DFF) to be used in the low-speed biomedical applications. The ADC can work between 0 to 1 MS/s. The prototype ADC fabricated in UMC 65 nm 1P6M CMOS achieves best performance at 25 kS/s with 50.1 dB SNDR and 55.3 dB SFDR. Operating at 1 V supply and 25 kS/s, the ADC consumes 281 nW and exhibits a FOM of 43.3 fJ/conversion-step. The chip die area is 145 μm × 120 μm.