An efficient hardware-based fault diagnosis scheme for AES: performances and cost
An efficient hardware-based fault diagnosis scheme for AES: performances and cost
复制标题
一种高效的基于硬件的 AES 故障诊断方案：性能和成本
DOI：
10.1109/dft.2004.8
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发表时间：
2004
期刊：
影响因子：
--
通讯作者：
P. Maistri
中科院分区：
文献类型：
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作者：
G. Bertoni;L. Breveglieri;I. Koren;P. Maistri
自2001年标准化以来，高级加密标准一直是许多研究工作的主题，旨在开发具有减少面积和延迟的高效硬件实现。到目前为止，可靠性还没有被认为是一个主要目标。最近，已经提出了几种错误检测方案，以提供对AES中的硬件故障的一些防御。这样的方案的好处是双重的：避免错误的输出时，良性的硬件故障发生，并防止通过恶意注入故障的秘密密钥的信息的收集。在本文中，我们提出了一个完整的方案，基于奇偶校验的故障检测的硬件实现的高级加密标准，其中包括一个关键的调度单元。我们还提供了一个初步的评估所提出的方案的硬件和延迟开销。
Since standardization in 2001, the Advanced Encryption Standard has been the subject of many research efforts, aimed at developing efficient hardware implementations with reduced area and latency. So far, reliability has not been considered a primary objective. Recently, several error detecting schemes have been proposed in order to provide some defense against hardware faults in AES. The benefits of such schemes are twofold: avoiding wrong outputs when benign hardware faults occur, and preventing the collection of information about the secret key through malicious injection of faults. In this paper, we present a complete scheme for parity-based fault detection in a hardware implementation of the Advanced Encryption Standard which includes a key schedule unit. We also provide a preliminary evaluation of the hardware and latency overhead of the proposed scheme.