Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating
Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating
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非易失性%20内存中逻辑%20array%20处理器%20in%2090nm%20MTJ/MOS%20实现%2075%%20泄漏%20减少%20使用%20基于周期的%20power%20门控
DOI：
10.1109/isscc.2013.6487696
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发表时间：
2013
期刊：
影响因子：
--
通讯作者：
T. Hanyu
中科院分区：
文献类型：
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作者：
M. Natsui;D. Suzuki;N. Sakimura;R. Nebashi;Y. Tsuji;A. Morioka;T. Sugibayashi;S. Miura;H. Honjo;K. Kinoshita;S. Ikeda;T. Endoh;H. Ohno;T. Hanyu
非易失性内存逻辑（NV-LIM）架构[1]，其中磁隧道结（MTJ）器件[2]分布在CMOS逻辑电路平面上，具有克服严重功耗问题的潜力，功耗问题已迅速成为当今VLSI处理器性能改进的主要制约因素。由于上述结构中MTJ器件的非挥发性和三维可堆叠性，具有小面积损失的正常关断和瞬时通能力，使我们能够在精细的时间粒度中应用功率门控技术，从而可以完美地消除由于漏电流造成的功耗浪费。然而，将非易失性存储设备嵌入逻辑电路的影响，仅通过使用小型制造的原始逻辑电路元件[3]、类似存储器的结构（如FPGA[4]）或电路模拟来证明，因为缺乏反映芯片制造环境的既定的面向mtj的设计流程，而更大容量和/或高速访问的MRAM已日益发展。在本文中，我们提出了一种MTJ/ mos混合视频编码硬件，该硬件使用基于周期的功率门控技术用于实用规模的基于MTJ的NV-LIM LSI，该LSI完全使用已建立的半自动化面向MTJ的设计流程进行设计。
Nonvolatile logic-in-memory (NV-LIM) architecture [1], where magnetic tunnel junction (MTJ) devices [2] are distributed over a CMOS logic-circuit plane, has the potential of overcoming the serious power-consumption problem that has rapidly become a dominant constraint on the performance improvement of today's VLSI processors. Normally-off and instant-on capabilities with a small area penalty due to non-volatility and three-dimensional-stackability of MTJ devices in the above structure allow us to apply a power-gating technique in a fine temporal granularity, which can perfectly eliminate wasted power dissipation due to leakage current. The impact of embedding nonvolatile memory devices into a logic circuit was, however, demonstrated by using only small fabricated primitive logic-circuit elements [3], memory-like structures such as FPGA [4], or circuit simulation because of the lack of an established MTJ-oriented design flow reflecting the chip-fabrication environment, while larger-capacity and/or high-speed-access MRAM has been increasingly developed. In this paper, we present an MTJ/MOS-hybrid video coding hardware that uses a cycle-based power-gating technique for a practical-scale MTJ-based NV-LIM LSI, which is fully designed using the established semi-automated MTJ-oriented design flow.