Design of Self-Timed Reconfigurable Controllers for Parallel Synchronization via Wagging
Design of Self-Timed Reconfigurable Controllers for Parallel Synchronization via Wagging
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DOI：
10.1109/tvlsi.2014.2306176
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发表时间：
2015-02
影响因子：
2.8
通讯作者：
J. Guido;A. Yakovlev
中科院分区：
文献类型：
--
作者：
J. Guido;A. Yakovlev
Synchronization is an important issue in modern system design as systems-on-chips integrate more diverse technologies, operating voltages, and clock frequencies on a single substrate. This paper presents a methodology for the design and implementation of a self-timed reconfigurable control device suitable for a parallel cascaded flip-flop synchronizer based on a principle known as wagging, through the application of distributed feedback graphs. By modifying the endpoint adjacency of a common behavior graph via one-hot codes, several configurable modes can be implemented in a single design specification, thereby facilitating direct control over the synchronization time and the mean-time between failures of the parallel master-slave latches in the synchronizer. Therefore, the resulting implementation is resistant to process nonidealities, which are present in physical design layouts. This paper includes a discussion of the reconfiguration protocol, and implementations of both a sequential token ring control device, and an interrupt subsystem necessary for reconfiguration, all simulated in UMC 90-nm technology. The interrupt subsystem demonstrates operating frequencies between 505 and 818 MHz per module, with average power consumptions between 70.7 and 90.0 μW in the typical-typical case under a corner analysis.
