Kickback noise reduction techniques for CMOS latched comparators
Kickback noise reduction techniques for CMOS latched comparators
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DOI：
10.1109/tcsii.2006.875308
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发表时间：
2006-07-01
影响因子：
4.4
通讯作者：
Vital, Joao C.
中科院分区：
文献类型：
--
作者：
Figueiredo, Pedro M.;Vital, Joao C.
锁存比较器是几乎所有模数转换器架构的组成部分。它采用正反馈机制将模拟输入信号重新生成为满量程数字电平。内部节点中的大电压变化耦合到输入端，干扰输入电压，这通常称为反冲噪声。本简介回顾了现有的解决方案，以尽量减少反冲噪声。并提出了两个新的。HSPICE模拟比较器实现了0.18 μ m的技术证明了它们的有效性。
The latched comparator is a building block of virtually all analog-to-digital converter architectures. It uses a positive feedback mechanism to regenerate the analog input signal into a full-scale digital level. The large voltage variations in the internal nodes are coupled to the input, disturbing the input voltage-this is usually called kickback noise. This brief reviews existing solutions to minimize the kickback noise. and proposes two new ones. HSPICE simulations of comparators implemented in a 0.18-mu m technology demonstrate their effectiveness.