iELAS: An ELAS-Based Energy-Efficient Accelerator for Real-Time Stereo Matching on FPGA Platform
iELAS: An ELAS-Based Energy-Efficient Accelerator for Real-Time Stereo Matching on FPGA Platform
复制标题
iELAS:基于 ELAS 的节能加速器,用于 FPGA 平台上的实时立体匹配
DOI:
10.1109/aicas51828.2021.9458401
复制
发表时间:
2021
期刊:
影响因子:
--
通讯作者:
A. Raychowdhury
中科院分区:
文献类型:
--
作者:
Tianren Gao;Zishen Wan;Yuyang Zhang;Bo Yu;Yanjun Zhang;Shaoshan Liu;A. Raychowdhury
Stereo matching is a critical task for robot navigation and autonomous vehicles, providing the depth estimation of surroundings. Among all stereo matching algorithms, Efficient Large-scale Stereo (ELAS) offers one of the best tradeoffs between efficiency and accuracy. However, due to the inherent iterative process and unpredictable memory access pattern, ELAS can only run at 1.5-3 fps on high-end CPUs and difficult to achieve real-time performance on low-power platforms. In this paper, we propose an energy-efficient architecture for real-time ELAS-based stereo matching on FPGA platform. Moreover, the original computational-intensive and irregular triangulation module is reformed in a regular manner with points interpolation, which is much more hardware-friendly. optimizations, including memory management, parallelism, and pipelining, are further utilized to reduce memory footprint and improve throughput. Compared with Intel i7 CPU and the state-of-the-art $\mathrm{C}\mathrm{P}\mathrm{U}+$FPGA implementation, our FPGA realization achieves up to $ 38.4\times$ and $ 3.32\times$ frame rate improvement, and up to $ 27.1\times$ and $ 1.13\times$ energy efficiency improvement, respectively.
影响因子:
9.2
作者:
Geiger, A.;Lenz, P.;Urtasun, R.
通讯作者:
Urtasun, R.