Bit-Width Allocation for Hardware Accelerators for Scientific Computing Using SAT-Modulo Theory
Bit-Width Allocation for Hardware Accelerators for Scientific Computing Using SAT-Modulo Theory
复制标题
使用 SAT 模理论进行科学计算的硬件加速器的位宽分配
DOI：
10.1109/tcad.2010.2041839
复制
发表时间：
2010
影响因子：
2.9
通讯作者：
N. Nicolici
中科院分区：
文献类型：
--
作者：
A. Kinsman;N. Nicolici
本文研究了应用程序的计算方法，通过可满足性模理论（SMT）的位宽分配问题，有限精度的数值计算的实现，特别是在科学计算的情况下，除法经常发生。与大量的工作针对精度方面的问题，本文解决的范围问题，采用SMT导致更准确的边界估计比其他分析方法提供的，反过来又产生更小的位宽，从而减少硬件成本和/或增加并行性，同时保持鲁棒性是必要的科学应用。
This paper investigates the application of computational methods via Satisfiability Modulo Theory (SMT) to the bit-width allocation problem for finite precision implementation of numerical calculations, specifically in the context of scientific computing where division frequently occurs. In contrast to the large body of work targeted at the precision aspect of the problem, this paper addresses the range problem where employing SMT leads to more accurate bounds estimation than those provided by other analytical methods, in turn yielding smaller bit-widths, and hence a reduction in hardware cost and/or increased parallelism, while maintaining robustness as is necessary for scientific applications.