Stored-sequence sigma-delta fractional-N synthesiser
Stored-sequence sigma-delta fractional-N synthesiser
复制标题
存储序列 sigma-delta 小数 N 合成器
DOI：
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发表时间：
2004
期刊：
影响因子：
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通讯作者：
R. Walkington
中科院分区：
文献类型：
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作者：
P. Brennan;R. Walkington
本文介绍了一种新的方法，sigma-delta分数-N频率合成的基础上存储的预生成的比特流。通过利用跳频系统的性质，可以完全避免制造硬件Σ-Δ调制器，而是将每个所需信道的优化Σ-Δ序列存储在快速存储器中。这允许几百MHz的参考频率，这提供了调制器的噪声扩展性能的显著增加。本文介绍了这样的合成器的模拟和实现。建模和测量结果表明，性能的大幅改善是可能的。
The paper describes a new approach to sigma-delta fractional-N frequency synthesis based on the storage of pre-generated bitstreams. By exploiting the nature of frequency hopping systems, fabrication of a hardware sigma-delta modulator can be avoided completely and instead an optimised sigma-delta sequence for each required channel is stored in fast memory. This allows reference frequencies of several hundred MHz, which provides a significant increase in the noise spreading performance of the modulator. The paper describes simulation and implementation of such a synthesiser. Both modelled and measured results are shown to demonstrate that a substantial improvement in performance is possible.