Test Architecture for Fine Grained Capture Power Reduction
Test Architecture for Fine Grained Capture Power Reduction
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DOI：
10.1109/icecs46596.2019.8964790
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发表时间：
2019-11
期刊：
影响因子：
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通讯作者：
Yi Sun;Hui Jiang;L. Ramakrishnan;Matan Segal;Kundan Nepal;Jennifer Dworak;T. Manikas;R. I. Bahar-R.-I.
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文献类型：
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作者：
Yi Sun;Hui Jiang;L. Ramakrishnan;Matan Segal;Kundan Nepal;Jennifer Dworak;T. Manikas;R. I. Bahar-R.-I.
在现场测试期间，功率过大会导致多种问题，包括测试结果无效、过热和电路损坏。在本文中，我们评估了当扫描链的特定片段可以保持不捕获受制于存储在控制寄存器中的值的数据时，捕获功率的降低。所提出的方法不需要对自动测试模式生成（ATPG）进行更改，不需要重新设计电路以匹配特定的测试集，也不需要额外的模式来维持故障覆盖。我们将展示我们的方法可以实现非常高的捕获功率降低-对于多种模式接近100%。
Excessive power during in–field testing can cause multiple issues, including invalidation of the test results, over- heating, and damage to the circuit. In this paper, we evaluate the reduction of capture power when specific segments of a scan chain can be kept from capturing data subject to values stored in a control register. The proposed approach requires no changes to the Automatic Test Pattern Generation (ATPG), no redesign of the circuitry to match a particular test set, and no additional patterns to maintain fault coverage. We will show that our approach can achieve very high capture power reduction-approaching 100% for multiple patterns.