Self-Measurement of Combinatorial Circuit Delays in FPGAs
Self-Measurement of Combinatorial Circuit Delays in FPGAs
复制标题
FPGA 中组合电路延迟的自测量
DOI：
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发表时间：
2009
期刊：
影响因子：
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通讯作者：
P. Cheung
中科院分区：
文献类型：
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作者：
Justin S. J. Wong;N. P. Sedcole;P. Cheung
本文提出了一种内建自测试（BIST）方法来精确测量FPGA上的组合电路延迟。在现代FPGA中发现的片上时钟生成能力的灵活性被用于步进通过一系列频率，直到检测到组合电路中的定时故障。这样，任何组合电路的延迟都可以用皮秒量级的定时分辨率来确定。并行和优化的实现方法的自表征的延迟的所有LUT上的FPGA也提出了。该方法已应用于Altera Cyclone II和III FPGA。在2.5秒内完成了Cyclone II上LUT的完整自表征，仅使用13kbit的块RAM存储结果。在Cyclone III上进行了更广泛的测试，并成功地测量了加法器电路和嵌入式乘法器模块的延迟。这种自测量方法为匹配FPGA设计中的时序要求铺平了道路，从而解决了工艺变化问题。
This article proposes a Built-In Self-Test (BIST) method to accurately measure the combinatorial circuit delays on an FPGA. The flexibility of the on-chip clock generation capability found in modern FPGAs is employed to step through a range of frequencies until timing failure in the combinatorial circuit is detected. In this way, the delay of any combinatorial circuit can be determined with a timing resolution of the order of picoseconds. Parallel and optimized implementations of the method for self-characterization of the delay of all the LUTs on an FPGA are also proposed. The method was applied to Altera Cyclone II and III FPGAs . A complete self-characterization of LUTs on a Cyclone II was achieved in 2.5 seconds, utilizing only 13kbit of block RAM to store the results. More extensive tests were carried out on the Cyclone III and the delays of adder circuits and embedded multiplier blocks were successfully measured. This self-measurement method paves the way for matching timing requirements in designs to FPGAs as a means of combating the problem of process variations.