Complementary-SCR ESD protection circuit with interdigitated finger-type layout for input pads of submicron CMOS IC's
Complementary-SCR ESD protection circuit with interdigitated finger-type layout for input pads of submicron CMOS IC's
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DOI：
10.1109/16.391212
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发表时间：
1995-07
影响因子：
3.1
通讯作者：
M. Ker;Chung-Yu Wu
中科院分区：
文献类型：
--
作者：
M. Ker;Chung-Yu Wu
提出了一种采用互补可控硅结构和结二极管的新型ESD保护电路。采用LDD工艺，在0.6 /spl mu/m CMOS SRAM技术上成功地制作并验证了这种具有交叉指型布局的互补可控硅ESD保护电路。通过基极-发射极短路方法，提出的ESD保护电路可以在5v VDD工作下免于VDD- vss锁存。为了弥补基极-发射极短路方法对ESD保护电路中横向可控硅器件锁相能力的降低，减小横向可控硅器件中横向BJT的p-井至p-井间距，以降低其ESD触发电压，提高横向可控硅器件中正反馈再生的导通速度。这种ESD保护电路可以在小布局区域的高ESD失效阈值下工作，因此非常适合用于高引脚数或高密度应用的亚微米CMOS VLSI/ULSI。>
A new ESD protection circuit with complementary SCR structures and junction diodes is proposed. This complementary-SCR ESD protection circuit with interdigitated finger-type layout has been successfully fabricated and verified in a 0.6 /spl mu/m CMOS SRAM technology with the LDD process. The proposed ESD protection circuit can be free of VDD-to-VSS latchup under 5 V VDD operation by means of a base-emitter shorting method. To compensate for the degradation on latching capability of lateral SCR devices in the ESD protection circuit caused by the base-emitter shorting method, the p-well to p-well spacing of lateral BJT's in the lateral SCR devices is reduced to lower its ESD-trigger voltage and to enhance turn-on speed of positive-feedback regeneration in the lateral SCR devices. This ESD protection circuit can perform at high ESD failure threshold in small layout areas, so it is very suitable for submicron CMOS VLSI/ULSI's in high-pin-count or high-density applications. >