AMBA to SoCWire network on Chip bridge as a backbone for a Dynamic Reconfigurable Processing unit

AMBA to SoCWire network on Chip bridge as a backbone for a Dynamic Reconfigurable Processing unit
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AMBA 到 SoCWire 芯片桥接网络作为动态可重配置处理单元的骨干

DOI:
10.1109/ahs.2011.5963941
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发表时间:
2011
期刊:
2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)
影响因子:
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通讯作者:
S. Habinc
S. Habinc
中科院分区:
--
文献类型:
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作者:
Holger Michel;F. Bubenhagen;B. Fiethe;H. Michalik;B. Osterloh;Wayne Sullivan;A. Wishart;J. Ilstad;S. Habinc

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航天器上的仪器或甚至完整的有效载荷数据处理单元通常由专用数据处理单元控制。该数据处理单元对子系统和遥控指令处理进行控制,并处理所获得的科学数据。随着探测器分辨率和测量速度的提高,处理需求也在迅速增长。为了在有限的功率预算的约束下满足这些日益增长的需求,作为片上系统(SoC)的专用硬件设计(例如,在FPGA中)已被证明是可行的解决方案。在以前的文章[1],[2]中,我们已经提出了我们的片上网络(NoC)解决方案SoCWire作为一个高效和可靠的方法,用于动态可重构架构。然而,控制任务仍然需要能够执行软件的顺序处理器。LEON处理器是一种适合太空应用的容错版本处理器,并且可以作为开源设计访问。本文提出了一种有效的解决方案相结合的片上网络和经典的基于处理器总线的通信架构,即AHB2SOCW桥作为一个有效的连接之间的SoCWire网络和LEON处理器总线系统。直接存储器访问使AHB2SOCW桥能够有效地工作。资源利用率和可获得的数据速率,以及预期的目标应用,这是一个有效的SoC控制器的可重构处理平台的基础上FPGA的前景。
Instruments on spacecrafts or even complete payload data handling units are typically controlled by a dedicated data processing unit. This data processing unit exercises control of subsystems and telecommand processing as well as processing of acquired science data. With increasing detector resolutions and measurement speeds the processing demands are rising rapidly. To fulfill these increasing demands under the constraints of limited power budgets, a dedicated hardware design as a System on Chip (SoC), e.g. in a FPGA, has been shown to be a viable solution. In previous papers [1], [2] we have presented our Network on Chip (NoC) solution SoCWire as a higly efficient and reliable approach for a dynamic reconfigurable architectures. However, the control task still requires a sequential processor which is able to execute software. The LEON processor is a processor that is available in a fault tolerant version suitable for space applications and is accessible as an open source design. This paper presents an efficient solution for a combined NoC and classic processor bus-based communication architecture, i.e. the AHB2SOCW bridge as an efficient connection between a SoCWire network and a LEON processor bus systems. Direct memory access enables the AHB2SOCW bridge to operate efficiently. The resource utilization and obtainable data rates are presented as well as an outlook for the intended target application, which is an efficient SoC controller for a reconfigurable processing platform based on FPGAs.