AMBA to SoCWire network on Chip bridge as a backbone for a Dynamic Reconfigurable Processing unit
AMBA to SoCWire network on Chip bridge as a backbone for a Dynamic Reconfigurable Processing unit
复制标题
AMBA 到 SoCWire 芯片桥接网络作为动态可重配置处理单元的骨干
DOI:
10.1109/ahs.2011.5963941
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发表时间:
2011
期刊:
影响因子:
--
通讯作者:
S. Habinc
中科院分区:
文献类型:
--
作者:
Holger Michel;F. Bubenhagen;B. Fiethe;H. Michalik;B. Osterloh;Wayne Sullivan;A. Wishart;J. Ilstad;S. Habinc
Instruments on spacecrafts or even complete payload data handling units are typically controlled by a dedicated data processing unit. This data processing unit exercises control of subsystems and telecommand processing as well as processing of acquired science data. With increasing detector resolutions and measurement speeds the processing demands are rising rapidly. To fulfill these increasing demands under the constraints of limited power budgets, a dedicated hardware design as a System on Chip (SoC), e.g. in a FPGA, has been shown to be a viable solution. In previous papers [1], [2] we have presented our Network on Chip (NoC) solution SoCWire as a higly efficient and reliable approach for a dynamic reconfigurable architectures. However, the control task still requires a sequential processor which is able to execute software. The LEON processor is a processor that is available in a fault tolerant version suitable for space applications and is accessible as an open source design. This paper presents an efficient solution for a combined NoC and classic processor bus-based communication architecture, i.e. the AHB2SOCW bridge as an efficient connection between a SoCWire network and a LEON processor bus systems. Direct memory access enables the AHB2SOCW bridge to operate efficiently. The resource utilization and obtainable data rates are presented as well as an outlook for the intended target application, which is an efficient SoC controller for a reconfigurable processing platform based on FPGAs.