Post-layout transistor sizing for power reduction in cell-based design
Post-layout transistor sizing for power reduction in cell-based design
复制标题
布局后晶体管尺寸可降低基于单元的设计中的功耗
DOI：
10.1109/aspdac.2001.913333
复制
发表时间：
2001
期刊：
影响因子：
--
通讯作者：
H. Onodera
中科院分区：
文献类型：
--
作者：
M. Hashimoto;H. Onodera
我们提出了一种晶体管尺寸调整方法，可缩小单元内 MOSFET 的尺寸，以尽可能消除基于单元的电路的冗余。我们的方法减少了详细布线电路的功耗，同时保留了互连。使用五个电路对我们方法的有效性进行了实验评估。功耗最大降低 77%，平均降低 65%，且延迟不增加。
We propose a transistor sizing method that downsizes MOSFETs inside a cell to eliminate redundancy of cell-based circuits as much as possible. Our method reduces power dissipation of detail-routed circuits while preserving interconnects. The effectiveness of our method is experimentally evaluated using five circuits. The power dissipation is reduced by 77% maximum and 65% on average without delay increase.