A second generation charge integrator and encoder ASIC
A second generation charge integrator and encoder ASIC
复制标题
第二代电荷积分器和编码器 ASIC
DOI：
10.1109/nssmic.1995.504226
复制
发表时间：
1995
期刊：
影响因子：
--
通讯作者：
M. Sarraj
中科院分区：
文献类型：
--
作者：
T. Zimmerman;M. Sarraj
第二代电荷积分器和编码器ASIC（QIE 5）已被设计用于费米实验室的KTeV实验。它旨在与FADC（通常为8位）结合使用，以快速的速率对光电倍增管（PMT）电流脉冲进行采样，并在16位动态范围内具有可变分辨率。QIE5在8个不重叠的二进制标度范围内集成了峰值高达30 ma的脉冲。高达53 MHz的系统时钟控制积分周期和读出速率。该器件采用流水线设计，因此没有信号死区时间。对于每个时钟周期，根据信号幅度选择一个范围，该范围的输出路由到QIE5模拟输出，并馈送到FADC以形成尾数。所选范围被编码并作为三位数字指数输出。使用这种方法，测量分辨率是在大动态范围内的信号的相对恒定的分数。之前的报告描述了具有固有局限性的单端器械（QIE2）。QIE5是一个完全差分设计，并包含许多其他功能，提供显着的性能改进。新的设计理念和测试结果是第一次。
A second generation charge integrator and encoder ASIC (QIE5) has been designed for the KTeV experiment at Fermilab. It is intended to be used in conjunction with a FADC (typically eight bits) to digitize photomultiplier tube (PMT) current pulses at a fast rate, with variable resolution over a 16 bit dynamic range. QIE5 integrates pulses of up to 30 ma peak on eight nonoverlapping binary scaled ranges. A system clock of up to 53 MHz controls the integration period and readout rate. The device is pipelined so that there is no signal deadtime. For each clock period, one range is selected depending on the signal magnitude, and the output of that range is routed to the QIE5 analog output and fed to the FADC to form the mantissa. The selected range is encoded and output as a three bit digital exponent. With this method, the measurement resolution is a relatively constant fraction of the signal over a large dynamic range. Previous reports have described a single ended device (QIE2) which had inherent limitations. The QIE5 is a fully differential design and contains numerous other features which provide significant performance improvements. The new design philosophy and test results are presented for the first time.