Reducing power consumption in FPGA routing

Reducing power consumption in FPGA routing
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降低 FPGA 布线中的功耗

DOI：
10.1109/ccece.2003.1226332
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发表时间：
2003
期刊：
CCECE 2003 - Canadian Conference on Electrical and Computer Engineering. Toward a Caring and Humane Technology (Cat. No.03CH37436)
影响因子：
--
通讯作者：
E. Esmaili
E. Esmaili
中科院分区：
--
文献类型：
--
作者：
M. S. Zamani;E. Esmaili

文献摘要

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现场可编程门阵列的主要缺点之一是它们的低能效。本文重点研究FPGA设计中的布线阶段，并尝试优化FPGA互连中的动态功耗。功率优化是在对电路性能和面积有小的副作用的情况下进行的。我们对VPR时序驱动算法的改进使FPGA布线功耗降低了约10%，而电路性能的损失可以忽略不计。
One of the major drawbacks of field programmable gate arrays is their poor energy efficiency. This paper focuses on the routing phase of FPGA design and attempts to optimize dynamic power consumption in FPGA interconnect. Power optimization is performed with small side effects on circuit performance and area. Our enhancements to the VPR timing driven algorithm reduced the FPGA routing power by about 10% with negligible loss in circuit performance.