Preventing Coherence State Side Channel Leaks Using TimeCache
Preventing Coherence State Side Channel Leaks Using TimeCache
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DOI：
10.1109/tc.2022.3209922
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发表时间：
2023-02
影响因子：
3.7
通讯作者：
Divya Ojha;S. Dwarkadas
中科院分区：
文献类型：
--
作者：
Divya Ojha;S. Dwarkadas
在共享内存存在的情况下，缓存侧通道攻击已被用于提取加密密钥和飞地数据，并被Spectre变体用于泄漏推测加载的数据。由于缓存数据和未缓存数据的响应延迟不同，共享缓存中存在定时侧通道。在以前的工作中，我们提出了TimeCache，一个缓存设计，防止侧通道利用共享内存的重用。在这项工作中，我们扩展TimeCache也防御攻击，利用一致性状态。TimeCache允许所有正在运行的应用程序使用整个缓存，避免了为了实现定时隔离而进行分区的需要。每进程缓存上下文防止缓存命中由另一个进程填充的数据。一种新颖的位串行时间戳并行比较逻辑允许陈旧的缓存上下文的低开销更新。该防御适用于所有缓存级别，并防御运行在任何核心上的攻击者。我们使用gem5模拟器来评估TimeCache，以表明它能够防止重用攻击和基于一致性状态泄漏的攻击。SPEC2006的平均性能开销为1.13%，PARSEC和SPLASH的平均性能开销为0.46%。
Cache side channel attacks in the presence of shared memory have been used to extract cryptographic keys and enclave data, and are used by Spectre variants for leaking speculatively loaded data. Timing side channels exist in shared caches due to the difference in response latency of cached and uncached data. In prior work, we presented TimeCache, a cache design that prevents side channel exploits from reuse of shared memory. In this work, we extend TimeCache to also defend against attacks that exploit coherence states. TimeCache allows all running applications to use the entire cache, avoiding the need for partitioning in order to effect timing isolation. A per-process caching context prevents cache hits on data filled by another process. A novel bit-serial timestamp-parallel comparison logic allows low-overhead update of stale caching contexts. The defense is suited to all caches levels, and defends against an attacker running on any core. We evaluate TimeCache using the gem5 simulator to show that it is capable of preventing both reuse attacks and an attack based on coherence state leak. The average performance overhead for SPEC2006 is 1.13%, and for PARSEC and SPLASH is 0.46%.