The ALPIDE pixel sensor chip for the upgrade of the ALICE Inner Tracking System
The ALPIDE pixel sensor chip for the upgrade of the ALICE Inner Tracking System
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DOI：
10.1016/j.nima.2016.05.016
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发表时间：
2017-02
影响因子：
1.4
通讯作者：
G. Rinella
中科院分区：
文献类型：
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作者：
G. Rinella
ALPIDE芯片是一种CMOS单片有源像素传感器，正在为欧洲核子研究中心大型强子对撞机的ALICE实验的ITS升级而开发。ALPIDE芯片采用180 nm CMOS成像工艺，并在具有高电阻率外延层的衬底上制造。它的尺寸为15 mm×30 mm，包含一个512×1024像素的矩阵，具有像素内放大、整形、鉴别和多事件缓冲功能。敏感矩阵的读出是命中驱动的。如果不存在要读出的命中并且功耗与占用成比例，则在矩阵上不存在信令活动。该传感器满足探测效率大于99%、假命中概率小于10− 5、空间分辨率为5 μm的实验要求。提供了在100 kHz下读出Pb-Pb相互作用的能力。预计ALPIDE芯片的功率密度对于内筒层中的应用小于35 mW/cm 2，对于外筒层中的应用小于20 mW/cm 2，其中占用率较低。本文描述了最终ALPIDE芯片的架构和主要功能，计划于2016年初提交。早期的结果，从实验资格的全尺寸原型前辈也报告。
The ALPIDE chip is a CMOS Monolithic Active Pixel Sensor being developed for the Upgrade of the ITS of the ALICE experiment at the CERN Large Hadron Collider. The ALPIDE chip is implemented with a 180 nm CMOS Imaging Process and fabricated on substrates with a high-resistivity epitaxial layer. It measures 15 mm×30 mm and contains a matrix of 512×1024 pixels with in-pixel amplification, shaping, discrimination and multi-event buffering. The readout of the sensitive matrix is hit driven. There is no signaling activity over the matrix if there are no hits to read out and power consumption is proportional to the occupancy. The sensor meets the experimental requirements of detection efficiency above 99%, fake-hit probability below 10−5and a spatial resolution of 5 μm. The capability to read out Pb–Pb interactions at 100 kHz is provided. The power density of the ALPIDE chip is projected to be less than 35 mW/cm2for the application in the Inner Barrel Layers and below 20 mW/cm2for the Outer Barrel Layers, where the occupancy is lower. This contribution describes the architecture and the main features of the final ALPIDE chip, planned for submission at the beginning of 2016. Early results from the experimental qualification of full scale prototype predecessors are also reported.