Partitioning techniques for partially protected caches in resource-constrained embedded systems
Partitioning techniques for partially protected caches in resource-constrained embedded systems
复制标题
资源受限嵌入式系统中部分受保护缓存的分区技术
DOI：
10.1145/1835420.1835423
复制
发表时间：
2010
期刊：
影响因子：
--
通讯作者：
N. Venkatasubramanian
中科院分区：
文献类型：
--
作者：
Kyoungwoo Lee;Aviral Shrivastava;N. Dutt;N. Venkatasubramanian
随着技术规模的成倍增长，即使在深亚纳米技术制造的嵌入式系统中，软错误率也将成为一个严重的设计考虑因素。部分保护缓存（PPC）是一个有前途的微体系结构功能，以减轻由于软错误的功耗，性能和成本敏感的嵌入式处理器的故障。具有PPC的处理器维护两个高速缓存，一个受保护，另一个不受保护，两者都处于存储器层次结构的同一级别。PPC背后的直觉是，并非应用程序中的所有数据都同样容易出现软错误。通过查找并将更容易发生软错误的数据映射到受保护的高速缓存，并将错误恢复数据映射到不受保护的高速缓存，可以以最小的功率和性能损失显著减少由软错误引起的故障。因此，PPC的有效性关键取决于编译器将应用程序数据划分为易出错数据和容错数据的能力。PPC的有效性已经在多媒体应用中得到了证明，其中存在明显的数据分区，多媒体数据固有地对软错误有弹性，并且其余的数据和整个代码被认为是容易出错的。由于多媒体数据量是整个应用程序数据的相当重要的组成部分，因此这种明显的分区是相当有效的。然而，对于一般的应用程序，不存在这样明显的数据和代码划分。这严重限制了PPC对一般数据高速缓存和指令高速缓存的适用性。本文研究了基于可扩展性的分区方案，这些方案适用于一般的应用程序，并以最小的功耗和性能开销有效地减少了由于软错误而导致的故障。
我们的实验结果与PPC架构增强的惠普iPAQ类处理器，运行从MiBench套件的基准测试表明，我们的分区启发式有效地发现数据PPC的页面分区，可以减少故障率48%，只有2%的性能和7%的能源开销，并找到指令PPC的页面分区，平均只需2%的性能和8%的能源开销即可将故障率降低50%。
Increasing exponentially with technology scaling, the soft error rate even in earth-bound embedded systems manufactured in deep subnanometer technology is projected to become a serious design consideration. Partially protected cache (PPC) is a promising microarchitectural feature to mitigate failures due to soft errors in power, performance, and cost sensitive embedded processors. A processor with PPC maintains two caches, one protected and the other unprotected, both at the same level of memory hierarchy. The intuition behind PPCs is that not all data in the application is equally prone to soft errors. By finding and mapping the data that is more prone to soft errors to the protected cache, and error-resilient data to the unprotected cache, failures induced by soft errors can be significantly reduced at a minimal power and performance penalty. Consequently, the effectiveness of PPCs critically hinges on the compiler's ability to partition application data into error-prone and error-resilient data. The effectiveness of PPCs has previously been demonstrated on multimedia applications—where an obvious partitioning of data exists, the multimedia data is inherently resilient to soft errors, and the rest of the data and the entire code is assumed to be error-prone. Since the amount of multimedia data is a quite significant component of the entire application data, this obvious partitioning is quite effective. However, no such obvious data and code partitioning exists for general applications. This severely restricts the applicability of PPCs to data caches and instruction caches in general. This article investigates vulnerability-based partitioning schemes that are applicable to applications in general and effectively reduce failures due to soft errors at minimal power and performance overheads.
Our experimental results on an HP iPAQ-like processor enhanced with PPC architecture, running benchmarks from the MiBench suite demonstrate that our partitioning heuristic efficiently finds page partitions for data PPCs that can reduce the failure rate by 48% at only 2% performance and 7% energy overhead, and finds page partitions for instruction PPCs that reduce the failure rate by 50% at only 2% performance and 8% energy overhead, on average.
搜索与 B/R4RGS 结合的支架蛋白
DOI：
--
发表时间：
2006
期刊：
影响因子：
--
作者：
藤井 聖司;牟田 貴里子;齊藤 修
通讯作者：
齊藤 修