Large-scale circuit placement
Large-scale circuit placement
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大规模电路布局
DOI：
10.1145/1059876.1059886
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发表时间：
2005
期刊：
影响因子：
--
通讯作者：
Xin Yuan
中科院分区：
文献类型：
--
作者：
J. Cong;J. Shinnerl;M. Xie;Tim Kong;Xin Yuan
放置是RTL-to-GDSII合成过程中最重要的步骤之一，因为它直接定义了互连，它们已成为深层亚微米技术中电路和系统性能的瓶颈。在过去的30年中，已经对位置问题进行了广泛的研究。但是，最近的研究表明，现有的放置解决方案远非最佳。本教程的第一部分总结了现有位置工具的最佳最佳性和可扩展性研究的结果。这些研究表明，来自行业和学术界的领先安置工具的结果可能高达50％。至150和百分比；远离总线长度的最佳。如果可以缩小这样的差距，相应的性能提高将等效于几个技术生成的进步。教程的第二部分突出了大规模电路放置上的最新进展，包括线长度最小化，路由性优化和性能优化的技术。
Placement is one of the most important steps in the RTL-to-GDSII synthesis process, as it directly defines the interconnects, which have become the bottleneck in circuit and system performance in deep submicron technologies. The placement problem has been studied extensively in the past 30 years. However, recent studies show that existing placement solutions are surprisingly far from optimal. The first part of this tutorial summarizes results from recent optimality and scalability studies of existing placement tools. These studies show that the results of leading placement tools from both industry and academia may be up to 50&percent; to 150&percent; away from optimal in total wirelength. If such a gap can be closed, the corresponding performance improvement will be equivalent to several technology-generation advancements. The second part of the tutorial highlights the recent progress on large-scale circuit placement, including techniques for wirelength minimization, routability optimization, and performance optimization.