A Fault Tolerant Parallelism Approach for Implementing High-Throughput Pipelined Advanced Encryption Standard
A Fault Tolerant Parallelism Approach for Implementing High-Throughput Pipelined Advanced Encryption Standard
复制标题
一种用于实现高吞吐量流水线高级加密标准的容错并行方法
DOI：
10.1142/s0218126616501139
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发表时间：
2016
期刊：
影响因子：
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通讯作者：
S. Hessabi
中科院分区：
文献类型：
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作者：
Hadi Mardani Kamali;S. Hessabi
高级加密标准（AES）是最流行的对称加密方法，它使用对称密钥对数据流进行加密。当前较优的AES架构采用有效方法来实现两个重要目标：抵御功耗分析攻击以及实现高吞吐量。基于不同的架构视角，我们为实现后一个目标实施了一种特殊的并行架构，该架构能够在现场可编程门阵列（FPGA）中实现更高效的流水线操作。在这方面，所有对展开主循环有作用的中间寄存器都将被移除。此外，我们不是展开AES算法的主循环，而是通过复制非流水线AES架构并为每个AES模块使用自动分配器机制来实现流水线结构。通过实施新的流水线架构，我们获得了两个有价值的优势：（a）当复制的部分之一出现故障时解决单点故障问题；（b）将所提出的设计部署为一种容错的AES架构。此外，我们强调对所有四个AES主要功能进行面积优化，以减少与AES模块复制相关的开销。仿真结果表明，我们所提出的AES架构的最大频率为675.62[公式：见原文]MHz，对于AES128，吞吐量为86.5[公式：见原文]Gbps，比最接近的现有竞争对手高出30.9%。
Advanced Encryption Standard (AES) is the most popular symmetric encryption method, which encrypts streams of data by using symmetric keys. The current preferable AES architectures employ effective methods to achieve two important goals: protection against power analysis attacks and high-throughput. Based on a different architectural point of view, we implement a particular parallel architecture for the latter goal, which is capable of implementing a more efficient pipelining in field-programmable gate array (FPGA). In this regard, all intermediate registers which have a role for unrolling the main loop will be removed. Also, instead of unrolling the main loop of AES algorithm, we implement pipelining structure by replicating nonpipelined AES architectures and using an auto-assigner mechanism for each AES block. By implementing the new pipelined architecture, we achieve two valuable advantages: (a) solving single point of failure problem when one of the replicated parts is faulty and (b) deploying the proposed design as a fault tolerant AES architecture. In addition, we put emphasis on area optimization for all four AES main functions to reduce the overhead associated with AES block replication. The simulation results show that the maximum frequency of our proposed AES architecture is 675.62[Formula: see text]MHz, and for AES128 the throughput is 86.5[Formula: see text]Gbps which is 30.9% better than its closest existing competitor.