Transition analysis on FPGA for multiplier-block based FIR filter structures
Transition analysis on FPGA for multiplier-block based FIR filter structures
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DOI：
10.1109/icecs.2000.913012
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发表时间：
2000-12
期刊：
影响因子：
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通讯作者：
S. Demirsoy;A. Dempster;I. Kale
中科院分区：
文献类型：
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作者：
S. Demirsoy;A. Dempster;I. Kale
本文研究了几种基于乘法器块的FIR滤波器结构的功耗分析。在FPGA器件上实现的滤波器结构的转换已经被计算在内。对产生乘法器块的算法进行了功率性能的比较。一个新的术语，故障路径计数，已经提出和测试使用作为一个指标的功耗。与加法器计数和逻辑深度方法相比，这种方法与转换计数的相关性更大。
This paper presents a study on the power consumption analysis of several multiplier-block based FIR filter structures. Transitions have been counted for the filter structures that were implemented on an FPGA device. The algorithms employed to generate the multiplier-blocks are compared with respect to their power performance. A new term, Glitch Path count, has been proposed and tested for use as an indicator of power consumption. This measure has been shown to be more correlated with the transition counts than the adder-count and logic depth approaches.