A -244dB-FOM High-Frequency Piezoelectric Resonator-Based Cascaded Fractional-N PLL with Sub-ppb-Order Channel Adjusting Technique
A -244dB-FOM High-Frequency Piezoelectric Resonator-Based Cascaded Fractional-N PLL with Sub-ppb-Order Channel Adjusting Technique
复制标题
基于-244dB-FOM高频压电谐振器的级联分数N PLL，具有亚ppb级通道调整技术
DOI：
10.1109/jssc.2016.2637001
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发表时间：
2017
影响因子：
5.4
通讯作者：
Kazuya Masu
中科院分区：
文献类型：
--
作者：
Sho Ikeda;Hiroyuki Ito;Akifumi Kasamatsu;Yosuke Ishikawa;Takayoshi Obara;Naoki Noguchi;Koji Kamisuki;Yao Jiyang;Shinsuke Hara;Dong Ruibing;Shiro Dosho;Noboru Ishihara;Kazuya Masu
提出了一种基于高频压电谐振器（PZR）的级联小数N分频锁相环（PLL）。子ppb级的频率分辨率是通过通道调整技术实现的。除了外形尺寸小之外，千兆赫频率下的高PZR还可实现RF应用中的极低相位噪声合成器。然而，三个基本问题仍然有待解决：窄调谐范围和大的工艺变化的PZR为基础的振荡器，参考千兆赫阶频率的PLL的低频率分辨率，和不希望的谐波振荡所造成的CMOS-PZR键合线的电感。为了克服这些问题，我们提出了一种通道调整技术（CAT），自适应地设置两个PLL的分频比，以保持恒定的输出频率的第二个PLL，而变化的PZR振荡器的频率，从而允许窄的调谐范围和宽的工艺变化的PZR振荡器。我们的PLL架构中的第一个PLL决定输出频率分辨率，第二个PLL降低三角积分调制器的功耗。我们还抑制了PZR振荡器中的谐波振荡。原型PLL采用65 nm CMOS制造，实现8.484-8.912 GHz输出、180 fs rms抖动和−244 dB FOM，功耗为12.7 mW。本文提出了一种基于亚ppb阶CAT的高频PZR的级联小数N分频锁相环，克服了千兆赫兹PZR调谐范围窄的问题。采用65 nm CMOS工艺制作的锁相环原型功耗为12.7 mW，输出频率为8.484-8.912 GHz，均方根抖动为180 fs。
This paper proposes a cascaded fractional-N phase-locked loop (PLL) based on a high-frequency piezoelectric resonator (PZR). Sub-ppb-order frequency resolution is achieved by a channel adjustment technique. Besides its small form factor, a high-PZR at gigahertz frequencies realizes a very low phase-noise synthesizer for RF applications. However, three fundamental issues remain to be solved: the narrow tuning range and large process variation of PZR-based oscillators, the low-frequency resolution of a PLL referenced to gigahertz-order frequencies, and the undesirable harmonic oscillation caused by the inductance of the CMOS-PZR bonding wire. To overcome these issues, we propose a channel-adjusting technique (CAT) that adaptively sets the division ratio of two PLLs to maintain constant output frequency of the second PLL while varying the PZR oscillator frequency, hence permitting the narrow tuning range and wide process variation of the PZR oscillator. The first PLL in our PLL architecture determines the output frequency resolution and the second reduces the power consumption of the delta–sigma modulator. We also suppress the harmonic oscillations in the PZR oscillator. The prototype PLL is fabricated in a 65-nm CMOS and achieves an 8.484–8.912-GHz output, 180-fs rms jitter, and −244-dB FOM while consuming 12.7-mW power. We developed a cascaded fractional-N PLL based on a high-frequency PZR with a sub-ppb-order CAT, which overcomes the narrow tuning range problem in gigahertz PZRs. A prototype PLL fabricated in a 65-nm CMOS consumed 12.7 mWand output 8.484–8.912 GHz with 180-fs rms jitter.