A jitter equalization technique for minimizing supply noise induced jitter in high speed serial links
A jitter equalization technique for minimizing supply noise induced jitter in high speed serial links
复制标题
一种抖动均衡技术，可最大限度地减少高速串行链路中电源噪声引起的抖动
DOI：
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发表时间：
2014
期刊：
影响因子：
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通讯作者：
Y. Ke
中科院分区：
文献类型：
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作者：
Yujeong Shim;D. Oh;T. Hoang;Y. Ke
随着串行接口数据速率的急剧提高，时序裕度越来越紧。根据硅制程技术，供电电压也在不断降低。然而，由于更高的数据速率、庞大的晶体管数量和封装技术的缓慢改进，电源噪声很难降低。因此，与其他抖动元件相比，由电源噪声引起的抖动可能相当大。由于PDN谐振频率高于CDR或PLL的环路带宽，因此接收器上的CDR或PLL无法抵消电源噪声引起的抖动。仅采用PDN改进来降低电源噪声引起的抖动是不符合成本效益的。优化电路和PDN等架构级的性能至关重要。本文提出了一种减小高速串行接口中电源噪声引起的抖动的新技术。所提出的技术称为抖动均衡器（JEqualizer），在最小的功率增加和头部面积的情况下，将抖动性能提高了80%。通过电源噪声诱发抖动模型对影响进行了评估。
As data rate of serial interface has increased dramatically, timing margin has gotten tighter and tighter. Supply voltage has also kept deducing according to silicon process technology. However, supply noise is hardly reduced due to higher data rate, a huge number of transistors and slower improvement of packaging technology. Therefore, the jitter due to supply noise can be quite large compared to other jitter components. The jitter due to supply noise is not cancelled out by CDR or PLL at the receiver since PDN resonance frequency is higher than loop bandwidth of CDR or PLL. It is not cost effective if only PDN improvement is adopted to reduce supply noise induced jitter. It is essential to optimize performance at architecture level including circuits and PDN. In this paper, the new technique is proposed to minimize supply noise induced jitter in high speed serial interface. The proposed techniques called Jitter Equalizer (JEqualizer) improves jitter performance by 80% with minimal power increase and area over head. The impact is evaluated by supply noise induced jitter modeling.