Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor
Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor
复制标题
具有双电源电压微处理器的片上集成降压转换器分析
DOI：
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发表时间：
2003
影响因子：
2.8
通讯作者：
E. Friedman
中科院分区：
文献类型：
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作者：
V. Kursun;S. Narendra;V. De;E. Friedman
本文对片上降压转换器进行了分析。高开关频率是同时实现单片集成和高效率的关键设计参数。开发了降压转换器的寄生阻抗模型。通过该模型，确定了设计空间，允许将有源和无源器件集成在同一芯片上以实现目标技术。在 477 MHz 开关频率下，1.2-0.9 伏电压转换的效率为 88.4%，同时提供 9.5 A 平均电流。假设采用 80 nm CMOS 技术，降压转换器占用的面积为 12.6 mm/sup 2/。效率估计值与目标设计点的仿真误差在 2.4% 以内。事实证明，将高效降压转换器与双 V/sub DD/微处理器完全集成在同一芯片上是可行的。
An analysis of an on-chip buck converter is presented in this paper. A high switching frequency is the key design parameter that simultaneously permits monolithic integration and high efficiency. A model of the parasitic impedances of a buck converter is developed. With this model, a design space is determined that allows integration of active and passive devices on the same die for a target technology. An efficiency of 88.4% at a switching frequency of 477 MHz is demonstrated for a voltage conversion from 1.2-0.9 volts while supplying 9.5 A average current. The area occupied by the buck converter is 12.6 mm/sup 2/ assuming an 80-nm CMOS technology. An estimate of the efficiency is shown to be within 2.4% of simulation at the target design point. Full integration of a high-efficiency buck converter on the same die with a dual-V/sub DD/ microprocessor is demonstrated to be feasible.