Evaluation of High-Speed Interfaces for VLSI Systems Using Tomlinson-Harashima Precoding
Evaluation of High-Speed Interfaces for VLSI Systems Using Tomlinson-Harashima Precoding
复制标题
使用 Tomlinson-Harashima 预编码评估 VLSI 系统的高速接口
DOI：
10.1109/ismvl.2014.32
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发表时间：
2014
期刊：
影响因子：
--
通讯作者：
Y. Yuminaka
中科院分区：
文献类型：
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作者：
Yosuke Iijima;Y. Yuminaka
互连的数据速率已成为实现超大规模集成（VLSI）系统高性能的重要因素。然而，超大规模集成电路系统中的微带线和带状线等互连很难实现高速数据传输。在高速数据速率下，互连表现为低通滤波器，会导致符号间干扰 (ISI) 并在接收器处引入误码。本文提出了使用 Tomlinson-Harashima 预编码 (THP) 技术的 4 脉冲幅度调制 (PAM)（4 值）信令的高速数据传输。为了实现THP电路，需要数字乘法和加法。为了评估硬件成本，我们研究了 THP 所需的位分辨率。理论分析和仿真结果表明，6 至 8 位数字分辨率对于消除微带线 2 [m] 上 3 Gbps 的 2-PAM（二进制）中足够量的 ISI 是必要的。
The data rate of interconnection has become an important factor in the achievement of high performance with very-large-scale integration (VLSI) systems. However, high-speed data transmission is difficult to achieve across interconnections such as microstrip lines and strip lines in VLSI systems. At high-speed data rates, interconnections behave as low-pass filters that cause intersymbol interference (ISI) and introduce bit errors at receivers. This paper proposes high-speed data transmission of 4-pulse amplitude modulation (PAM) (4-valued) signaling, using a Tomlinson-Harashima precoding (THP) technique. To realize the THP circuitry, digital multiplication and addition are required. To evaluate hardware costs, we investigate the required bit resolution for THP. Theoretical analysis and simulation results show that 6- to 8-bit digital resolution is necessary to remove a sufficient amount of ISI in 2-PAM (binary) at 3 Gbps over a microstrip line 2 [m].