Supply and threshold-Voltage trends for scaled logic and SRAM MOSFETs
Supply and threshold-Voltage trends for scaled logic and SRAM MOSFETs
复制标题
缩放逻辑和 SRAM MOSFET 的电源和阈值电压趋势
DOI：
--
复制
发表时间：
2006
影响因子：
3.1
通讯作者：
Fumitomo Matsuoka
中科院分区：
文献类型：
--
作者：
E. Morifuji;Takeshi Yoshida;Masahiko Kanda;Satoshi Matsuda;Seiji Yamada;Fumitomo Matsuoka
作者从低功耗的角度为逻辑块和高密度SRAM单元的V/sub dd/和阈值电压（V/sub th/）缩放提供了新的指导方针。对于逻辑运算，他们估计了扇出=3的反相器门的功率和速度。他们发现，最佳的V/sub dd/是非常敏感的开关活动，除了工作频率。他们建议在芯片上集成两组具有不同V/sub dd/s的晶体管。在具有高频率或高开关活动的芯片部分中，使用V/sub dd/和V/sub th/适度缩放的H晶体管是有帮助的。另一方面，在低开关活动块或相对低频率部分中，使用V/sub dd/应该保持在1- 1.2V左右的L晶体管是有利的。H和L的组合有利于抑制未来的功耗。他们研究了SRAM阵列的产量，以研究SRAM操作的最佳V/sub dd/。在高密度SRAM中，由于低静态噪声容限和高位泄漏，特别是在高温操作下，低V/sub th/导致成品率损失和面积损失。从面积大小的角度来看，V/sub th/应保持在0.3-0.4 V左右。在这项研究中，SRAM操作的最小V/sub dd/被发现是0.7 V。还发现SRAM的电源电压不能连续缩放。
The authors show new guidelines for V/sub dd/ and threshold voltage (V/sub th/) scaling for both the logic blocks and the high-density SRAM cells from low power-dissipation viewpoint. For the logic operation, they have estimated the power and the speed for inverter gates with a fanout=3. They find that the optimum V/sub dd/ is very sensitive to switching activity in addition to the operation frequency. They propose to integrate two sets of transistors having different V/sub dd/s on a chip. In portions of the chip with high frequency or high switching activity, the use of H transistors in which V/sub dd/ and V/sub th/ are moderately scaled is helpful. On the other hand, in low switching activity blocks or relatively low frequency portions, the use of L transistors in which V/sub dd/ should be kept around 1-1.2 V is advantageous. A combination of H and L is beneficial to suppress power consumption in the future. They have investigated the yield of SRAM arrays to study the optimum V/sub dd/ for SRAM operation. In high-density SRAM, low V/sub th/ causes yield loss and an area penalty because of low static noise margin and high bit leakage especially at high temperature operation. V/sub th/ should be kept around 0.3-0.4 V from an area size viewpoint. The minimum V/sub dd/ for SRAM operation is found to be 0.7 V in this study. It is also found that the supply voltage for SRAM cannot be scaled continuously.