Investigation of Low-Energy Tilted Ion Implantation for Fin-Type Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor Extension Doping
Investigation of Low-Energy Tilted Ion Implantation for Fin-Type Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor Extension Doping
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DOI：
10.1143/jjap.49.04dc18
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发表时间：
2010-01-01
影响因子：
1.5
通讯作者：
Masahara, Meishoku
中科院分区：
文献类型：
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作者：
Liu, Yongxun;Matsukawa, Takashi;Masahara, Meishoku
通过在不同I/I条件下制备一系列n(+)-多晶硅（poly-Si）栅极n沟道FinFET，系统地研究了fin型双栅金属氧化物半导体场效应晶体管（FinFET）源漏扩展掺杂的低能倾斜离子注入（I/I）。利用导通状态电流（I- on）与关断状态电流（I- off）以及SD寄生电阻（R-p）对所制备器件的性能进行基准测试，以研究在固定低能量5 keV下的最佳扩展I/I条件，包括剂量(D)和倾斜角度（θ）。实验发现，最佳扩展I/I条件为D = 4 × 10(14) cm（-2）和θ = 60°。随着D的进一步增大，器件性能下降，主要原因是在薄扩展区出现非晶区不完全再结晶。当θ = 0度时，由于植入原子从每个延伸区域随机散射，可见R-p有明显的增加和波动。在上述最佳I/I条件下制备的finfet的R-p值与由磷硅酸盐玻璃（PSG）荧光粉固相扩散制备的器件的R-p值相当。这表明D = 4 x 10(14) cm（-2）和θ = 60度的扩展I/I条件几乎是最佳的，并且对于高性能FinFET制造非常有效。(C) 2010日本应用物理学会
The low-energy tilted ion implantation (I/I) for fin-type double-gate metal-oxide-semiconductor field-effect transistor (FinFET) source-drain (SD) extension doping is systematically investigated experimentally by fabricating a series of n(+)-polycrystalline silicon (poly-Si) gate n-channel FinFETs under different I/I conditions. The on-state current (I-ON) versus off-state current (I-OFF) and the SD parasitic resistance (R-p) are used for benchmarking the performance of the fabricated devices to investigate the optimal extension I/I conditions, including dose (D) and tilted angle (theta), at a fixed low energy of 5 keV. It is experimentally found that the best extension I/I conditions are D = 4 x 10(14) cm(-2) and theta = 60 degrees. With further increasing D, the device performance deteriorates owing to the incomplete recrystallization of amorphous regions in the thin extension regions. In the case of theta = 0 degrees, marked increment and fluctuations in R-p are observed because the implant atoms scatter out randomly from each extension region. The R-p value of the FinFETs fabricated under the above best I/I conditions is comparable to that of devices fabricated by the solid-phase diffusion of phosphors from phosphosilicate glass (PSG). This indicates that the extension I/I conditions of D = 4 x 10(14) cm(-2) and theta = 60 degrees are almost optimal and is very effective for high-performance FinFET fabrication. (C) 2010 The Japan Society of Applied Physics