Signature-Based SER Analysis and Design of Logic Circuits
Signature-Based SER Analysis and Design of Logic Circuits
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DOI：
10.1109/tcad.2008.2009139
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发表时间：
2009
影响因子：
2.9
通讯作者：
Smita Krishnaswamy;Stephen M. Plaza;I. Markov;J. Hayes
中科院分区：
文献类型：
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作者：
Smita Krishnaswamy;Stephen M. Plaza;I. Markov;J. Hayes
我们探索签名的使用，即，在软错误分析和逻辑合成期间，通过位并行功能仿真生成的部分真值表。首先，我们提出了一个基于签名的CAD框架，它结合了软错误率（x）的逻辑级分析和基于签名的可靠性设计（SiDeR）的工具。我们观察到，软错误率（SER）的逻辑电路是密切相关的各种可测性参数，如信号的可观测性和概率。我们表明，这些参数可以非常有效地计算（在线性时间）的签名。因此，AnSER评估逻辑掩蔽比其他SER评估器快两到三个数量级，同时保持准确性。AnSER还可以通过近似稳态概率和时序信号的可观测性来有效地计算时序电路中的SER。在本文的第二部分中，我们将AnSER逻辑综合设计流程，旨在可靠的电路设计。SiDeR识别和利用冗余已经存在于电路中通过签名比较，以减少SER。我们表明，SiDeR减少SER的40%，只有13%的面积开销。我们还描述了第二个基于签名的合成策略，采用本地重写，同时提高面积和减少SER。这种技术产生13%的减少SER与2%的面积减少。我们表明，结合这两种合成方法可以导致进一步的面积可靠性的改善。
We explore the use of signatures, i.e., partial truth tables generated via bit-parallel functional simulation, during soft error analysis and logic synthesis. We first present a signature-based CAD framework that incorporates tools for the logic-level analysis of soft error rate (x) and for signature-based design for reliability (SiDeR). We observe that the soft error rate (SER) of a logic circuit is closely related to various testability parameters, such as signal observability and probability. We show that these parameters can be computed very efficiently (in linear time) by means of signatures. Consequently, AnSER evaluates logic masking two to three orders of magnitude faster than other SER evaluators while maintaining accuracy. AnSER can also compute SER efficiently in sequential circuits by approximating steady-state probabilities and sequential signal observabilities. In the second part of this paper, we incorporate AnSER into logic synthesis design flows aimed at reliable circuit design. SiDeR identifies and exploits redundancy already present in a circuit via signature comparison to decrease SER. We show that SiDeR reduces SER by 40% with only 13% area overhead. We also describe a second signature-based synthesis strategy that employs local rewriting to simultaneously improve area and decrease SER. This technique yields 13% reduction in SER with a 2% area decrease. We show that combining the two synthesis approaches can result in further area-reliability improvements.