A high-linearity Vernier time-to-digital converter on FPGAs with improved resolution using bidirectional-operating Vernier delay lines
A high-linearity Vernier time-to-digital converter on FPGAs with improved resolution using bidirectional-operating Vernier delay lines
复制标题
FPGA 上的高线性游标时间数字转换器，使用双向操作游标延迟线提高分辨率
DOI：
10.1109/tim.2019.2959423
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发表时间：
2019
影响因子：
5.6
通讯作者：
Xiangyu Li（李翔宇）
中科院分区：
文献类型：
--
作者：
Ke Cui;Xiangyu Li（李翔宇）
时间数字转换器（TDC）是许多时序关键型系统的核心组件。抽头延迟线是基于现场可编程门阵列（FPGA）的TDC中应用最广泛的一种形式，但它存在非线性差、延迟线占用长等问题。最近，一种新的基于环形振荡器的游标TDC电路被证明具有更小的非线性和更短的延迟线。由于所使用的延迟线没有得到补偿，所以当振荡次数大时，定时抖动显著增加（或精度降低）。这将导致不期望的较低分辨率选择以保持可接受的精度。本文提出了一种新型的双向游标延迟线结构，以减少精细时间测量中所需的振荡次数。传统上，对于游标延迟线，快信号沿着慢延迟线传播，而慢信号沿着快延迟线传播，我们称之为普通游标延迟线。新结构提出了两条平行的Vernier延迟线，由一条正常的Vernier延迟线和另一条异常的Vernier延迟线组成。术语“异常”指的是快信号和慢信号被异常地分别馈送到快延迟线和慢延迟线。在Stratix III FPGA上实现了基于该方法的TDC原型电路。测试结果表明，采用该电路结构后，系统的分辨率和均方根误差均从30-40 ps提高到20-30 ps。
Time-to-digital converters (TDCs) act as a core component in many timing-critical systems. Tapped delay line is the most widely used style for the field-programmable gate-array (FPGA)-based TDCs, but it suffers from several intractable problems such as poor nonlinearity and long delay-line occupation. Recently, a new ring-oscillator-based Vernier TDC circuit using carry chains was demonstrated to have much smaller nonlinearity with a much shorter delay line. Since the used delay line is not compensated, the timing jitter increases (or the precision degrades) remarkably when the oscillation number is large. This would incur undesirable lower resolution selection to maintain acceptable precision. In this article, a novel bidirectional-operating Vernier delay line structure is proposed to reduce the required oscillation number during the fine time measurement. Traditionally, for the Vernier delay line, the fast signal propagates along the slow delay line, while the slow signal propagates along the fast delay line, to which we call the normal Vernier delay line. The new structure proposes two parallelized Vernier delay line, consisting of one normal Vernier delay line and another abnormal Vernier delay line. The term “abnormal” refers to that the fast and slow signals are unusually fed to the fast and slow delay lines, respectively. A prototype TDC circuit based on this new method was implemented on a Stratix III FPGA. Test results demonstrate that by adopting the proposed novel circuit architecture, both the resolution and the root-mean-square error can be improved from the 30–40-ps level to the 20–30-ps level.