A Practical Guide for SystemVerilog Assertions
A Practical Guide for SystemVerilog Assertions
复制标题
SystemVerilog 断言实用指南
DOI：
10.1007/b137011
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发表时间：
2005
影响因子：
--
通讯作者：
M. Ramanathan
中科院分区：
文献类型：
--
作者：
Srikanth Vijayaraghavan;M. Ramanathan
SystemVerilog语言由三类特性组成--设计、断言和测试平台。断言为ASIC验证过程增加了一个全新的维度。工程师们习惯于用verilog编写测试台来帮助验证他们的设计。Verilog是一种过程性语言，处理当今构建的复杂ASIC的能力非常有限。SystemVerilog Assertions(SVA)是一种声明性语言。该语言的时态特性提供了对时间的良好控制，并允许同时执行多个进程。这为工程师解决他们的验证问题提供了一个非常强大的工具。与标准的verilog语言相比，这种语言仍然是新的，从用户的角度来看，思维方式也有很大的不同。到目前为止，该领域还没有足够的专业知识或知识产权。虽然已经很好地定义了该语言，但没有实用指南来说明如何使用该语言来解决实际的验证问题。这本书是一本实用指南，将帮助人们理解这种新语言，并迅速采用基于断言的验证方法。
SystemVerilog language consists of threecategories of features-- Design, Assertions and Testbench. Assertions add a whole new dimension to the ASIC verification process.Engineers are used to writing testbenches in verilog that helpverify their design. Verilog is a procedural language and is very limited in capabilities to handle the complex ASICs built today. SystemVerilog assertions (SVA) is a declarative language. The temporal nature of the language provides excellent control over time and allows mulitple processes to execute simultaneously. This provides theengineers a very strong tool to solve their verification problems. The language is still new and the thinking is very different from theuser's perspective when compared to standard verilog language. There is not enough expertise or intellectual property available as of today in the field. While the language has been defined very well, there is no practical guide that shows how to use the language to solve real verification problems. This book is a practical guide that will help people to understand this new language and adopt assertion based verification methodology quickly.